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Since Ii = Io, changing Ii will effectively scale Io by that same factor. The question now is how to take our digital inputs and turn them into summable currents. Since each bit of the digital input carries a different weight as a factor of 2, we will need to add current into the input branch by a similar factor of 2. Let’s take a 1-bit digital code and build a DAC out of it. Suppose Ri and Ro are given the same value: R. Ro / Ri = R / R = 1. When Vi is high, Vo will match it. When Vi is low, Vo will also be low. Thus, we have a 1-bit DAC.
Let’s take into account 2 bits now. Bit 1 has a weight of 2^1, whereas Bit 0 has a weight of 2^0. In other words, the weight of Bit 0 is half that of Bit 1. If we treat these bits as input voltages, then the voltage when Bit 0 is high must have lower weight than input voltage of Bit 1. Since the high state of digital inputs have a fixed voltage that cannot be changed (such as 5V), our only option is to limit the current produced by the inputs instead. We can accomplish this by separating the input voltages by differently-weighted resistors that go into the same node. By doing so, the individual currents produced by the inputs can be summed before they reach the op-amp. Since the Bit 0 input needs to have half as much weight as Bit 1’s, we can reduce its current by half, which means doubling the resistance. So what we end up having is the Bit 1 input connected to a resistor of resistance R and the Bit 0 input connected to a resistor of resistance 2R. The R and 2R resistors are then connected by a node that goes into the negative terminal of the op-amp.
How about 3 bits? With Bit 2 having a weight of 2^2, it now has quadruple the weight of Bit 0. As such, the Bit 0 input voltage should only produce ¼ of the current that the Bit 2 input voltage can produce. In addition, Bit 1 has a weight of 2^1 and thus should produce half the current of Bit 2, but double the current of Bit 0. If we follow a similar procedure as the 2-bit DAC, we end up assigning the Bit 2 input to a resistor of resistance R, Bit 1 to a 2R resistor, and Bit 0 to a 4R resistor. Connecting all of these input pairs in parallel like before will give us a DAC that operates with three bits now.
If we keep adding more bits, then we need to add more resistor-input pairs. Adding more pairs almost resembles adding more rungs to a ladder, hence why this DAC is known as a binary-weighted ladder. For this type of DAC, the basic composition relies on pairing the MSB voltage with a resistance R, pairing the next significant bit with a resistance of 2R, then the next significant bit gets 4R, and so on and so forth until the LSB is assigned a resistance of (2^(n-1))R.
The binary-weight ladder is a simple solution. Due to its simplicity, however, it has implementation issues. We need n resistors, all with different values. There is a big difference between the smallest and the largest resistor. Additionally, these resistor values have to be fairly accurate in order to maintain the current ratios/weights. Even being a few ohms off for one resistor can ultimately have a large impact on the output voltage of the DAC. If we pick R at a range that we can find high-quality low-error values, then 2^(n-1) R is going to be a very large resistor that might be harder to find or buy. For example, if n = 14 and we select a value of R such as 10 kΩ, finding a resistor with a value of (2^14)R or more than 160 MΩ can be challenging. The resistor attached to MSB should have the highest quality, but all resistors need to be accurate as well. However, there is another DAC structure we can use that eliminates this flaw.
(Source: https://www.electronics-tutorial.net/analog-integrated-circuits/data-converters/binary-weighted-resistor-dac/)
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