In UART, a single data symbol is comprised of only one bit. Thus, the baud rate in a UART system is equivalent to its bit rate (and bauds are equal to bits). So if the baud rate of a UART is 1000 bauds/sec, then the UART can transmit one bit in 1/1000 seconds = 1 millisecond. Suppose we have a UART with a baud rate of 1,000 bits/sec, and one device is sending a frame of data. The receiver must be operating at the same baud rate as the transmitter (in this case, 1,000 bits/sec) to avoid data corruption. When the receiver sees the falling edge (indicating that the data line has gone from idle to a start bit), it knows that each bit is 1 millisecond long. So upon seeing the falling edge, if the receiver waits 1 millisecond, then it knows that the next bit has arrived. And if the receiver waits another millisecond, the next bit afterward will arrive, and so on.

Now, the receiver knows how long it takes for each bit to arrive, but how will it know what the value of each bit is? Since the logic level for a single bit lasts for 1 millisecond (in this case), we will have to sample or get the value of the bit once in that 1 millisecond period. The question now is when to sample the bit. Sampling it on the edges of the cycle could lead to erroneous results since rising, or falling edges could appear. Thus, it is usually best to sample the bit in the middle of the cycle. So when the receiver sees the falling edge, it should wait for half a cycle (0.5 milliseconds) before waiting for a full cycle to start sampling bits.

The above example is for a [5O2] frame (five data bits, odd parity, and two stop bits) being transmitted at 1,000 bits/sec. When the receiver sees the falling edge, it waits 0.5 milliseconds. At this point, the receiver could sample the start bit, or it could opt not to. Regardless, the receiver waits for a full cycle from the middle of the start bit to reach the middle of the first data bit. At this point, it samples the first data bit. Then, it waits another 1 millisecond and samples the next bit. This process repeats until all the data bits, the parity bit, and the stop bits have been sampled. Then the data line goes back to idling. Since the packet size and format is predetermined, the bitstring received can then be parsed to extract the data.