Si/SiGe/Ge/III-V nanotube transistors

What is the future of computational technology?

Why not carbon nanotube (CNT) based electronics?

What inspired the concept of silicon (Si) nanotube transistor?

We introduced the concept of silicon nanotube field effect transistor whose unique core–shell gate stacks help achieving full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultra-thin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core–shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow.

H. M. Fahad, C. E. Smith, J. P. Rojas, M. M. Hussain

Silicon Nanotube Field Effect Transistor with Core-Shell Gate Stacks for Enhanced High Performance Operation and Area Scaling Benefits

Nano Lett., 2011, 11 (10), pp 4393–4399

DOI: 10.1021/nl202563s

Are Nanotube Architectures More Advantageous Than Nanowire Architectures For Field Effect Transistors?

Decade long research in 1D nanowire field effect transistors (FET) shows although it has ultra-low off-state leakage current and a single device uses a very small area, its drive current generation per device is extremely low. Thus it requires arrays of nanowires to be integrated together to achieve appreciable amount of current necessary for high performance computation causing an area penalty and compromised functionality. Here we show that a FET with a nanotube architecture and core-shell gate stacks is capable of achieving the desirable leakage characteristics of the nanowire FET while generating a much larger drive current with area efficiency. The core-shell gate stacks of silicon nanotube FETs tighten the electrostatic control and enable volume inversion mode operation leading to improved short channel behavior and enhanced performance. Our comparative study is based on semi-classical transport models with quantum confinement effects which offers new opportunity for future generation high performance computation.

H. M. Fahad, M. M. Hussain

Scientific Reports 2, Article number: 475 (2012)

doi:10.1038/srep00475

Can we overcome the performance limitation challenge in tunnel FETs?

To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET's effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultra-low off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs.

H. M. Fahad, M. M. Hussain

High Performance Silicon Nanotube Tunneling FET for Ultra-Low Power Logic Applications

Published in: IEEE Transactions on Electron Devices ( Volume: 60, Issue: 3, March 2013 ) Page(s): 1034 - 1039

DOI: 10.1109/TED.2013.2243151

Is the concept of nanotube with core-shell gate-stacks extendable to other materials such as hetero-structure material systems?

We discuss the physics of conventional channel material (silicon/germanium hetero-structure) based transistor topology mainly core/shell (inner/outer) gated nanotube vs. gate-all-around nanowire architecture for tunnel field effect transistor application. We show that nanotube topology can result in higher performance through higher normalized current when compared to nanowirearchitecture at Vdd = 1 V due to the availability of larger tunneling cross section and lower Shockley-Reed-Hall recombination. Both architectures are able to achieve sub 60 mV/dec performance for more than five orders of magnitude of drain current. This enables the nanotube configuration achieving performance same as the nanowire architecture even when Vdd is scaled down to 0.5 V.

A. N. Hanna, M. M. Hussain

Si/Ge hetero-structure nanotube tunnel field effect transistor

Journal of Applied Physics 117, 014310 (2015); https://doi.org/10.1063/1.4905423

How about III-V hetero-structure materials integrated nanotube FETs?

Hetero-structure tunnel junctions in non-planar gate-all-around nanowire (GAA NW) tunnel FETs (TFETs) have shown significant enhancement in ‘ON’ state tunnel current over their all-silicon counterpart. Here we show the unique concept of nanotube TFET in a hetero-structure configuration that is capable of much higher drive current as opposed to that of GAA NW TFETs.Through the use of inner/outer core-shell gates, a single III-V hetero-structured nanotube TFET leverages physically larger tunneling area while achieving higher driver current (ION) and saving real estates by eliminating arraying requirement. Numerical simulations has shown that a 10 nm thin nanotube TFET with a 100 nm core gate has a 5×normalized output current compared to a 10 nm diameter GAA NW TFET.

A. N. Hanna, H. M. Fahad, M. M. Hussain

InAs/Si Hetero-Junction Nanotube Tunnel Transistors

Scientific Reports 5, Article number: 9843 (2015)

doi:10.1038/srep09843

How can one make such transistor?