Why do we need to explore nanomaterials as future option for nanoelectronics?

Silicon has been working as the most reliable semiconductor material for computational technology. CMOS industry scaled transistors to sub-100 nm region decades back. In the last ten years, several major changes have taken place to continue the Moore's Law: introduction of high-k/metal gate stacks instead of silicon dioxide/poly silicon gate stacks (circa 2008) and introduction of non-planar 3D FinFET architecture (circa 2011). Although we are continuing scaling of transistor dimensions, soon enough from material perspective we will be facing road blocks to continue straight forward physical scaling. And thus, in the recent past, alternative channel materials have been explored: SiGe, Ge, GeSn and III-V materials. GeSn has been explored as a potential hole rich channel material for p-type Metal Oxide Semiconductor Field Effect Transistors (p-MOSFETs), using expensive Molecular Beam Epitaxy (MBE) and Metal Organic Chemical Vapor Deposition (MOCVD) equipment. Since, we do firmly believe cost-effectiveness is critical for CMOS technology, we decided to explore Silicon Tin (SiSn) as a potential electron rich channel material for n-MOSFETs. Also, we explored a set of relatively cost-effective process technologies like thin film deposition followed by thermal annealing for lamination. In a series of papers, we reported a theoretical analysis and experimental verification of change in band gap of silicon lattice due to the incorporation of tin (Sn). We formed SiSn ultra-thin film on the top surface of a 4 in. silicon wafer using thermal diffusion of Sn. We observed an increase of 13.6% in the average field effect hole mobility for SiSn devices compared to silicon control devices. We showed a reduction of 0.1 V in the average built-in potential, and a reduction of 0.2 V in the average reverse bias breakdown voltage, as measured across the substrate. These reductions indicated that the band gap of the silicon lattice had been reduced due to the incorporation of Sn, as expected from the theoretical analysis. We also demonstrated the experimentally calculated band gap of SiSn to be 1.11 ± 0.09 eV. This low-cost, CMOS compatible, and scalable process offers a unique opportunity to tune the band gap of silicon for specific applications. 

Is there a way we can lower the cost of traditionally epitaxial materials?

We have been always intrigued by the expensive nature and the high-quality of the epitaxially grown crystalline materials. It is understandable the quality comes with cost! Yet, we decided to explore whether germanium (one of the expensive materials) can be grown on bulk silicon (100) without deployment epitaxy process. We demonstrated a simple, low-cost, and scalable process for obtaining uniform, smooth surfaced, high quality mono-crystalline germanium (100) thin films on silicon (100). The germanium thin films were deposited on a silicon substrate using plasma-assisted sputtering based physical vapor deposition. They were crystallized by annealing at various temperatures ranging from 700 °C to 1100 °C. We report that the best quality germanium thin films are obtained above the melting point of germanium (937 °C), thus offering a method for in-situ Czochralski process. We show well-behaved high-κ /metal gate metal–oxide–semiconductor capacitors (MOSCAPs) using this film. 

Hussain, A. M., Fahad, H. M., Sevilla, G. A. T. and Hussain, M. M. (2013), Thermal recrystallization of physical vapor deposition based germanium thin films on bulk silicon (100). Phys. Status Solidi RRL, 7: 966–970. doi:10.1002/pssr.201308019

We also showed a complementary metal oxide semiconductor (CMOS) compatible fabrication of flexible metal–oxide–semiconductor capacitors (MOSCAPs) with high-κ/metal gate stack, using a physical vapor deposition (PVD) cost-effective technique to obtain a high-quality Ge channel. We report outstanding bending radius ∼1.25 mm and semi-transparency of 30%.

Nassar, J. M., Hussain, A. M., Rojas, J. P. and Hussain, M. M. (2014), Low-cost high-quality crystalline germanium based flexible devices. Phys. Status Solidi RRL, 08: 794–800. doi:10.1002/pssr.201409257 

Except channel material, what is the next major concern for nanoelectronics?

We say contact formation. It is highly critical to form a good metal/semiconductor contact. Due to scaling, overall contact area is decreasing and obviously the contact resistance is also increasing. And thus contact engineering has become more and more challenging over the years. We chronicled our understanding in two invited review papers: fundamentals of contact engineering, evolution into non-planar field effect transistors, opportunities and challenges with one and two-dimensional materials and a new opportunity of contact engineering from device architecture perspective. 

Why amorphous metal based nanostructures are critical for ultra-low power electronics?

While expansion of nanoelectronics through scaling is helping us to have enhanced performance of transistors, resulting in higher information processing speed, it comes with its short channel effects: increased power consumption even the devices are not working. And with increased global population, with increased usage of visual form of information, overall power consumption through variety of computational gadgets is much higher. And thus it is critical to look for alternate technologies which can offer ultra-low to zero (really?!) power consumption. Mechanical relay is an interesting choice as at its idle state, it is physically detached. However, mechanical movement makes them slower compared to charge transport based devices. For a little over a decade, scientific community has explored nano-scale relays. Interesting designs, modeling results followed by experimental demonstrations have been reported. Yet, one specific condition has been unsurpassed. Without having an amorphous conductive material as structural material it is really difficult to maintain the structural integrity at nano-scale. Because, grain size in crystalline material can sometimes be larger than the nano-scale dimensions needed on those devices. Many years back, Texas Instruments developed a highly complex but superbly effective amorphous metal for their amazingly successful MEMS product DLP technology (used in all the projectors in the past). Therefore, we decided to find out a low-cost simple amorphous metal for nano-scale electromechanical devices and obviously NEM switch is an interesting device to explore. We reported a three-terminal laterally actuated NEM switch fabricated with an amorphous metallic material: tungsten nitride (WNx ). As-deposited WNx thin films have high Young's modulus (300 GPa) and reasonably high hardness (3 GPa), which are advantageous for high wear resistance. The first prototype WN x switches are demonstrated to operate with relatively low control voltage, down to 0.8 V for an air gap thickness of 150 nm. We are immensely grateful to Prof. Tsu-Jae King Liu for her valuable advice regarding this paper.

A. M. Mayet, A. M. Hussain, M. M. Hussain, “3-Terminal Nanoelectromechanical Switch Based On Tungsten Nitride – An Amorphous Metallic Material”, Nanotechnology 27, 035202 (2016).

How do we feel about 2D materials as better alternate for crystalline material based nanoelectronics?

We consider 2D materials are interesting exploratory materials. We see their prospect in Radio Frequency (RF) electronics, in sensor technology as well as transparent conductive materials. Graphene as being one of the semi-metallic materials, forming a low-power transistor is highly challenging with it. Therefore, we showed integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11,000 cm2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low tox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance. 

C. Smith, R. Qaisi, Z. Liu, Q. Yu, M. M. Hussain*, “Low Voltage Back-gated Atmospheric Pressure Chemical Vapor Deposition based Graphene Striped Channel Transistor with High-k Dielectric Showing Room Temperature Mobility >11,000 cm2/V-s”, ACS Nano, 7(7), 5818–5823 (2013).

Also, graphene's transfer from growth site to destination site is quite random. "The curious" Ghoneim made a video based on his MS thesis work which has been viewed more than 35,000 times on graphene transfer ( 

M. T. Ghoneim, C. E. Smith, M. M. Hussain*, “Simplistic Graphene Transfer Process and Its Impact on Contact resistance”, Appl. Phys. Lett. 102, 183115 (2013).

Another question, that has come to our mind, is graphene high thermal budget compatible?

We reported the characteristics of atmospheric chemical vapor deposition grown bilayer graphene transistors fabricated on ultra-scaled (10 nm) high-κ dielectric aluminum oxide (Al2O3) at elevated temperatures. We observed that the drive current increased by >400% as temperature increased from room temperature to 250 °C. Low gate leakage was maintained for prolonged exposure at 100 °C but increased significantly at temperatures >200 °C. These results provide important insights for considering chemical vapor deposition graphene on aluminum oxide for high temperature applications where low power and high frequency operation are required. 

Qaisi, R. M., Smith, C. E. and Hussain, M. M. (2014), Atmospheric pressure chemical vapor deposition (APCVD) grown bi-layer graphene transistor characteristics at high temperature. Phys. Status Solidi RRL, 8: 621–624. doi:10.1002/pssr.201409100

Have we worked on dichalcogenide 2D materials?

Very limited. We still consider such materials are exploratory material which require uniform and reliable growth process, contact formation and many other challenges to be solved by Material Scientists, Chemists and Physicists.

Yet, Molybdenum disulphide (MoS2) is an emerging 2-dimensional (2D) semiconductor for electronic devices. However, unstable and low performance of MoS2 FETs is an important concern. We inserted an atomic layer deposition (ALD) titanium dioxide (TiO2) interfacial layer between contact metal and MoS2 channel is suggested to achieve more stable performances. The reduced threshold voltage (VTH) shift and reduced series resistance (RSD) were simultaneously achieved. 

W. Park, J. Min, S. Shaikh, M. M. Hussain*, “Stable MoS2 FETs using TiO2 Interfacial Layer at Metal/MoS2 Contact”, physica solidi status A  [Cover Article]