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A proud moment: introduction of high-k/metal gate-stack based planar and non-planar CMOS in main stream microprocessors (January 2007)
A proud moment: introduction of high-k/metal gate-stack based planar and non-planar CMOS in main stream microprocessors (January 2007)
M. M. Hussain*, C. E. Smith, R. Harris, C. Young, B. Sassman, H. –H. Tseng, , R. Jammy, “Gate First Integration of High-k/Metal Gate CMOS FinFET with Multi-VTh Engineering”, IEEE Trans. Elect. Dev. 57(3), 626–631 (2010).
A process integration marvel: the first ever gate-first integration of tunable work function metal gates of different thicknesses (3-20 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ~40 mV/V), nearly symmetric VTh, low Tinv (~1.4 nm), and high Ion (~780 uA/um) for N/PMOS without any intentional strain enhancement.
M. M. Hussain*, G. Gebara, S. Lanee, B. Sassman, L. Larson, ”Controlled Isotropic Dry Etch Based Nano-fabrication”, J. Vac. Sci. Technol. B 25, 1416 (2007).
Eventually awarded a US Patent (7,736,954), in this paper, we showed an overetch triggered undercutting to fabricate thin film nanowires on a silicon wafer. For the first time, batch-fabricated metallic nanowire—titanium nitride (TiN)—on 200mm200mm silicon wafers using highly selective, timed, isotropic dry etch is being reported. Use of conventional microfabrication in the author’s demonstrated technique indicates the simplicity and economy of fabricating nanowires.
M. M. Hussain*, Carolyn Gondran, Di Michelson, “3D Nanostructure Sidewall Study by Direct Measurement with Conventional Atomic Force Microscope”, Nanotechnology 18(33), 335303 (2007).
We present the use of direct measurements of sidewall surface structures by conventional atomic force microscopy (AFM) as an alternative or complementary method for studying multi-layer film stacks and as the preferred method for studying FinFET sidewall surface roughness.
M. M. Hussain*, G. Gebara, E. Labelle, B. Sassman, S. Lanee, N. Moumen, L. Larson “Deposition Thickness Based Metallic Nano-Imprint Mold”, Microelectr. Engr. 84(4), 594–598 (2007).
We showed a general fabrication method and fabricated nano-imprint templates with sub-15 nm template line width and 10 nm pitch length through out the entire 200 mm wafer, varying the deposition thickness of multiple alternate films, using atomic layer deposition.
M. M. Hussain*, M. Quevedo-Lopez, H. N. Alshareef, D. Larison, B. Gnade, M. El-Bouanani, “Thermal Annealing Effects on Physical Properties of a Representative High-k/Metal Film Stack”, Semicond. Sci. Technol. 21, 1437–1440 (2006).
In this paper, an atomic layer deposition (ALD)-based hafnium oxide (HfO2)/titanium nitride (TiN) film stack (representative of the high-k/metal film stack) was annealed at 1000 °C to determine any change in the physical and electrical properties, such as thickness, surface roughness, density, sheet resistance, refractive index, extinction coefficient, composition, C–V characteristics, work function and etch rate. Although there was no significant electrical impact, some significant physical changes have been observed, which impact the process of integrating high-k/metal film stacks, especially in dual metal gate CMOSs.
M. M. Hussain*, S. C. Song, J. Barnett, C. Y. Kang, B. Sassman, N. Moumen, ”Plasma Induced Damage in High-k/Metal Gate Stack Dry Etch”, IEEE Elect. Dev. Lett. 27(12), 972–974 (2006).
In this letter, a comparative study in the context of device performance has been conducted to compare dry etch versus wet etch for gate stack etch of hafnium oxide/tantalum silicon nitride gate stack. It has been found that the dry-etched gate stack exhibit significantly more gate leakage current and poorer uniformity in threshold-voltage distribution
M. M. Hussain*, M. Quevedo-Lopez, H. N. Alshareef, K. Mathur, B. Gnade, “Deposition Method Induced Stress Effects on Ultra-thin Titanium Nitride Etch Characteristics”, Electrochem. Solid-State Lett. 9(12), G361-G363 (2006).
This study eventually lead us to discover role of metal gate induced strain for performance enhancement in high-k/metal gate CMOS. Eventually adopted by Intel Corporation in all their microprocessors marketed since 2008.
A systematic study to investigate the fundamental cause for wet etch variation of ultrathin titanium nitride film as a function of the deposition technique such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition is presented. For this study, films were investigated using X-ray diffraction, X-ray photoelectron spectroscopy, X-ray reflectometry, and absolute ellipsometry. It is shown that the deposition method plays an important role on the final crystallography and properties. However, it is demonstrated that the dominating factor defining etch rate is the resulting film strain.
Two seminal papers documented an extensive (1500 experiments) result on integration strategy for high-k/metal gate CMOS.
M. M. Hussain*, N. Moumen, Z. Zhang, B. Womack, “Metal Wet Etch Issues and Effects in Dual Metal Gate Stack Integration”, J. Electrochem. Soc. 153, G389–G393 (2006).
M. M. Hussain*, N. Moumen, J. Barnett, J. Saulters, D. Baker, Z. Zhang, “Metal Wet Etch Process Development for Dual Metal Gate CMOS”, Electrochem. Solid-State Lett. 8, G333 (2005).
C. D. Young, K. Akarvardar, M. O. Baykan, K. Matthews, I. Ok, T. Ngai, K. –W. Ang, J. Pater, C. E. Smith, M. M. Hussain, P. Majhi, C. Hobbs, “(110) and (100) Sidewall-oriented FinFETs: A performance
C. D. Young, A. Neugroschel, K. Matthews, C. Smith, D. Heh, H. Park, M. M. Hussein, W. Taylor, G. Bersuker, “Gated Diode Investigation of Bias Temperature Instability in High-κ FinFETs”, IEEE Elect. Dev. Lett. 31(7), 653–655 (2010).
C. S. Park, M. M. Hussain, G. Bersuker, P. Kirsch, R. Jammy, “Characteristics of a band-edge p-channel metal-oxide-semiconductor-field-effect-transistors fabricated with a high-k/WAlx/TiSiN gatestack”, Appl. Phys. Lett. 97, 023501 (2010).
C. S. Park, P. Lysaght, M. M. Hussain, J. Huang, G. Bersuker, P. Majhi, P. D. Kirsch, H. H. Tseng, and R. Jammy, “Advanced High-k/Metal Gate Stack Progress and Challenges - A Materials and Process Integration Perspective”, Intl. J. Mater. Res. 101(2), 155-163 (2010).
H.-H. Tseng , P. Kirsch, C. S. Park, G. Bersuker, P. Majhi, M. Hussain, R. Jammy, “The progress and challenges of threshold voltage control of high-k/metal-gated devices for advanced technologies”, Microelectronic Engr. 86(7–9), 1722 (2009) [Invited Paper].
C. D. Young, J. –W. Yang, K. Matthews, S. Suthram, M. M. Hussain, G. Bersuker, C. Smith, R. Harris, R. Choi, B. H. Lee, H. –H. Tseng, “Hot carrier degradation in HfSiON-TiN fin shaped field effect transistor with different substrate orientations”, J. Vac. Sci. Technol. B: Microelect. Nanometer Struct. 27(1), 468 (2009).
S. Suthram, M. M. Hussain, H. R. Harris, C. Smith, H. –H. Tseng, R. Jammy, S. E. Thompson, “Comparison of Uniaxial Wafer Bending and Contact-Etch-Stop-Liner Stress Induced Performance Enhancement on Double-Gate FinFETs”, IEEE Elect. Dev. Lett. 29(5), 480–482 (2008).
P. D. Kirsch, P. Sivasubramani, J. Huang, C. D. Young, M. A. Quevedo-Lopez, H. C. Wen, H. Alshareef, K. Choi, C. S. Park, K. Freeman, M. M. Hussain, G. Bersuker, H. R. Harris, P. Majhi, R. Choi, P. Lysaght, B. H. Lee, H.-H. Tseng, R. Jammy, T. S. Böscke, D. J. Lichtenwalner, J. S. Jur, and A. I. Kingon, “Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning”, Appl. Phys. Lett. 92, 092901 (2008).
P. Majhi, P. Kalra, R. Harris, J. Oh, M. M. Hussain, H. -H. Tseng, R. Jammy, "CMOS Scaling Beyond High-k and Metal Gates", Future Fab Intl. 22, 80-84 (2007). [Invited paper]
R. Harris, M. M. Hussain, C. Smith, J. -W. Yang, P. Majhi, H. Adhikari, H. -H. Tseng, R. Jammy, “FinFETs: Challenges in Material and Processing for a New 3D Device Paradigm”, Future Fab Intl. 23, 09, (2007). [Invited paper]
R. Harris, M. Hussain, C. Smith, J-W. Yang, J. Barnett, B. Sassman, S. Song, B.H. Lee, H. –H. Tseng, R. Jammy, “Critical Components of FinFet Integration: Examining the Density Trade-off and Process Integration for FinFET Implementation”, ECS Trans. 11(6) 331 (2007). [Invited paper]
S. Song, M. Hussain, J. Barnett, C. S. Park, C. Park, P. Kirsch, B.H. Lee, R. Jammy, “Integration Challenges and Opportunities for Nanometer Scale CMOSFET with Metal/High-k Gate Stack”, ECS Trans. 11(6) 315 (2007). [Invited paper]
C. Y. Kang, R. Choi, M. M. Hussain, J. Wang, Y. J. Suh, H. C. Floresca, M. J. Kim, J. Kim, B. H. Lee, R. Jammy, “Effects of metal gate-induced strain on the performance of metal-oxide-semiconductor field effect transistors with titanium nitride gate electrode and hafnium oxide dielectric”, Appl. Phys. Lett. 91, 033511 (2007).
B. H. Lee, S. C. Song, R. Jammy, and M. Hussain, “Challenges in Dual Workfunction Metal Gate CMOS Integration”, ECS Trans. 3 (2) 263–274 (2006). [Invited paper]
J. Barnett, N. Moumen, J. Peterson, M. M. Hussain, S. C. Song, G. Bersuker, "Cleaning's Role in High-k/Metal Gate Success", Semicond. Intl. Feb (2006). [Invited paper]
S. C. Song, M. M. Hussain, J. Barnett, B. S. Ju, B. H. Lee, ”Advances and Challenges in Dual Work Function Metal Gate CMOS Integration”, Solid State Technol. Aug (2006) [Invited paper].
Z. Zhang, S. C. Song, C. Huffman, M. M. Hussain, J. Barnett, N. Moumen, H. Alshareef, P. Majhi, J. Sim, S. H. Bae, B. H. Lee, “Integration of Dual Metal Gate CMOS on High-k Dielectrics Utilizing a Metal Wet Etch Process”, Electrochem. Solid-State Lett. 8, G271 (2005).
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