VHDL, which stands for Very High Speed Integrated Circuit (VHSIC) Hardware Descriptive Language, is a hardware description language used in digital design and electronic design automation. It is a standardized language for describing the behavior of electronic circuits and systems.
VHDL was originally developed by the U.S. Department of Defense in the 1980s for documenting the behavior of Application-Specific Integrated Circuits (ASICs).
Key features of VHDL include the ability to describe both the behavior and structure of a digital circuit.
VHDL also supports simulation at various levels of abstraction, enabling designers to verify and debug their designs before actual implementation.
Additionally, VHDL is used for testbench development to validate the functionality of digital designs through simulation.
Overall, VHDL plays a crucial role in the field of digital design by providing a powerful and versatile means of describing, simulating, and synthesizing digital circuits.
In VHDL there are three levels of abstraction that allow designers to describe digital circuits at different levels of detail and complexity: Data Flow, Behavioral and Structural.
In Data Flow modeling, the circuit functionality is expressed in terms of basic logical operators. Conditional statements and signal assignment statements are common at this level.
Behavioral modeling focuses on the functionality or behavior of the digital circuit without specifying its internal structure. It describes what the circuit does rather than how it does it. If-else statements and case statements are the constructs which are predominantly used in this style.
Structural modeling provides a detailed structural description of the digital circuit, specifying how the circuit is composed of interconnected components such as gates, flip-flop, and multiplexers. Instantiation of components and the use of configuration declarations are the common constructs used in this level. It is analogous to functions and function calls in programming languages.
Every VHDL program has an entity and an architecture associated with it.
The entity describes the circuit interface while the architecture describes how modules are inputs and modules are connected.
No matter at what level of abstraction you want to write your VHDL code, the entity doesn't change. The three abstraction levels only differ in their architecture.
VHDL is a case-insensitive language.