Testbench

Writing a testbench for a structural code is exactly the same as writing a testbench for a data flow code. Therefore, it is suggested to look at the process to create a testbench here.

Note the difference in giving values for std_logic and std_logic_vector. For std_logic, we use single quotes for values ('0' or '1'). For std_logic_vector, we use double quotes ("1101" or "0101").

Your testbench will look something as follows.

The simulation window can be found below.

To aid visual verification, you may change the radix of the inputs of the outputs.

Several radix options are available in ModelSim. Some of them are Binary, Octal, Decimal, Unsigned, Hexadecimal, etc.

To change the radix, in the Wave window, right click on the variable and select the radix option. Change it as per your preference.