Testbench

Providing inputs manually using the Wave Editor in ModelSim is not efficient as you may not account for all the possible test cases.

Also the user has to manually search for all the combinations of inputs and it can be very frustrating.

Testbenches are a powerful alternative to verify your design as they can give you full control over the input stimulus.

Additionally, testbenches can be scripted and reused for various designs by making minimal modifications.

You may write a testbench in Quartus. However, testbenches cannot be synthesized. They can only be compiled.

Therefore, it is recommended to write testbenches directly in ModelSim.

After compiling your main VHDL entity file, launch ModelSim from the Windows Start Menu as shown below.

The following window opens up.

Go to File -> New -> Project.

Assign a Project Name of your choice.

Choose the Project location as the same folder where you have the main VHDL entity file.

Click on OK.

Add the existing VHDL file that is in the directory.

The file is added to the Project.

Now we have to create the VHDL file for writing the testbench.

Click on Create New File.

Assign filename as testbench.

Make sure the file type is VHDL.

Click on OK.

At this stage, you should see two files in the Project window as shown below.

You can close the Add items to the Project window.

Double click on testbench.vhd. The editor window opens. You may also double click on comb_logic to look at your original design file.

Lets begin writing the testbench.

In the first two lines, provide the library files as you did for the design file.

Next write the entity for the testbench. Note that the testbench has on inputs or outputs. This is because, your testbench is not the actual design file.

For the entity, you want to choose the same name that you gave for the filename. Therefore, the entity name will be testbench.

Next is the architecture for the testbench. It follows the same rules as shown in the main design file.

We need to include the entity of the main design file as a component that the testbench will make a function call to.

Copy the entity in your design file and paste it before the begin block.

Change entity to component.

Also add component after the end of entity.

Add the four signals which have to be mapped to the component. This is very similar to a standard function call.

You may choose to give different names. However, I prefer to use the same names as the ones in the component for consistency.

Next part is to call the component and provide input stimulus.

A function call in VHDL involves the name of the component and port mapping the signals as per order. Also a tag can be assigned to each call. Typically tag names are DUT (Device-Under-Test) and UUT (Unit-Under-Test). However, you are free to choose your own name.

Next step is to provide inputs.

Inputs are given in a process. A tag can be associated with every process just as we provided a tag for the function call. It can be of any name.

Every process has a begin-end block. Inputs are specified in this block.

Since the circuit has 3 inputs, there will be a total of 8 combinations. 

Separate each input combination by 10 ns. This means that the inputs are held constant for 10 ns. After 10 ns, the next set of inputs are applied.

Put a wait after the last combination. If you do not put it, the simulation runs indefinitely.

Now its time to compile the design file and testbench on ModelSim.

First compile the design file and then the testbench.

To compile, right click on the file -> Compile -> Compile Selected.

Errors (if any) are reported in the transcript window.

If compilation is successful, you will see the equivalent messages in the transcript window.

Also, you will see the status of both the files turn to green.

Now simulate the testbench.

To simulate the testbench, click on the testbench file.

Then go to Simulate -> Start Simulation.

Expand work. Choose testbench and click OK.

You should see the following screen.

Since you are checking 8 combinations of inputs and each combination holds for 10 ns, set the run time to 100 ns.

Select all the 4 signals in the blue Objects window.

Right click and select Add Wave. 

Click on the Run button just beside the run time window where you entered 100 ns.

You will now see the inputs and outputs.

If you are seeing straight lines, right click on the wave and Zoom Full.

Verify the circuit.