Structural VHDL

In structural VHDL, the design is described using interconnected components, much like a schematic representation of a circuit.

Focus is placed on the hierarchical organization of the design and interconnections among different components are explicitly specified.

In structural modeling, components are the basic building blocks. 

Components are reusable blocks defined by entities. They encapsulate the functionality of a particular part of a design.

Components are instantiated and connected to build the overall design.

Structural programming is very similar to Functions and Function Calls in high level programming languages such as C, C++, Python, etc.

Lets build an unsigned subtractor circuit. The circuit has two 4-bit inputs (A and B) and the output (F) is a 4-bit vector. The circuit performs A - B using 2's complement method. For simplicity, lets assume that the the value represented by A is always greater than or equal to the value of B. The circuit interface is given below.

Inside the square, the actual circuit is designed which consists of Full Adders and NOT gates. Typically, you are responsible for coming up with the circuit.

The actual circuit is given below. Note that A, B and F are vectors where (0) indicates the LSB and (3) indicates the MSB.

As you can see, the circuit consists of FA's and NOT gates which are interconnected.

The FA's and the NOT gates are components that can be built and called upon whenever required.

The main entity of the design is subtractor_circuit.

In structural modeling, each individual component is constructed and tested.

Once all components are available, they are called and interconnected in the main entity file.

Lets start building the components. Click here to learn about this process.