The Entity

Lets model the circuit shown below. 

After Creating a New Project, click on File -> New -> VHDL File.

A blank editor opens up as follows.

Click on File -> Save As. Your filename should be the same as your module name or entity name. In the circuit shown above, the module name is comb_logic.

The first step is to include the library files. This is similar to including header files in C language or packages in Python.

The library file that we want to include is the IEEE file. The IEEE library is a standard library that includes packages defining common datatypes, mathematical functions, and other utilities for digital design.

Within the IEEE library, the std_logic_1164 package is a widely used package that defines the std_logic type and provides functionalities for working with digital signals.

The std_logic type is a multi-valued logic type that includes Logic 0, Logic 1, High Impedance (Z) etc.

Therefore, the first two lines must be as shown below.

The next step is to write the entity.

An entity consists of the module name, port names, direction and type.

Module name is comb_logic.

The module has 4 ports: A, B, C and F.

A, B and C are input ports. F is the output port.

All the ports can only assume Boolean values (Logic 0 or Logic 1). Therefore, it is of type std_logic.

Combining all of these, the entity can be written as follows.

To learn about writing architecture for Data Flow modeling, click here.