Architecture - Data Flow

The first line describes the name of the architecture and also specifies the entity for which you want the architecture.

As shown below, the name of the architecture is flexible. You may choose to change it from dataflow to XYZ.

Every architecture will have a begin and an end. The description of the circuit is specified within this region.

Going back to the original circuit, we can come up with the Boolean expression F = AB + C.

In VHDL, the expression is written as F <= (A and B) or C; It is shown below. Save the file.

In most practical cases, it might not be feasible to write the entire Boolean expression due to it being too long.

In such cases, we can split up the logic.

For this, signal's are used.

The above circuit can be slightly modified to account for the signal as shown below.

Temp_AB is the new signal that we created which can be used to split the logic.

Signal are always declared in the architecture before the begin keyword as shown below.

Note that this signal is of type std_logic.

The signal is not the circuit input or output. Therefore, its direction must not be declared.

Any variables that are not input or output ports must be declared as signals.

Now the logic expressions can be written in the architecture as shown below.

Programming langauges process instructions sequentially. However, VHDL processes instructions parallelly. Therefore, the order of instructions is not significant.

Compile and Synthesize your code by clicking on Processing -> Start Compilation.

To simulate the design, you can either go with the same process as you did for Schematic Capture or you could do it more efficiently using testbenches.

To learn how to write a testbench for the above design, click here.