Architecture

Give the name of the architecture along with the entity name for which you are writing the architecture.

Next step is to include both the components (FA and NOT_Gate). To do this copy the entity of the FA and paste it before the begin keyword.

Change entity to component. Add end component at the end.

It should look as follows.

Include the NOT_Gate as a component as well. 

If you look at the design, the NOT gates are used to flip the bits of B.

To connect B(0) to the NOT gate (the component you created), we use port maps.

Every call to the component has 5 attributes.
1. Tag: You can give it any name that you like.
2. Component: The name of the component that you would like to call.
3. Map: Keywords port map.
4. Ports: Order of inputs and outputs. Be careful with this part. 

Note that we are making new signals here and they have to be declared before the begin keyword.

A sample is shown below. Note that you have to be specific in the order in which you are assigning the signals in port maps. Switching the inputs and outputs in port maps would give you an incorrect result.

Repeat the process for two more NOT gates.

There may be times when you would not prefer to create a separate component just for an AND gate or a NOT gate etc, as this can be easily incorporated without a component. Structural modeling and data flow modeling can be combined together. This is demonstrated for the last NOT gate.

Now invoke the FA's and port map the rest of the signals.

Note that the Carry Outs are declared as signals as these are not circuit inputs or inputs.

The first FA has '1' as one one of its input. Notice how it has been port mapped.

This completes the architecture.

Set it as the top-level entity and compile the code.

Make sure you check the compilation report to know if you are compiling the correct file.

If you want to look at the circuit that is created, go to Tools -> Netlist Viewers -> RTL Viewer. The entire design is now here. If you want to look inside a FA, double click on the block and you will see the internal circuit.

A design file shown in RTL Viewer can be found below. Take a special note of the last NOT gate highlighted in yellow. If you remember, this NOT gate was written as a data flow equation.