The Main Entity

Create another VHDL file. File -> New -> VHDL File.

A blank editor opens up. Click on File -> Save As -> subtractor_circuit.

The first step in writing the entity is to include the library files. If you have read the Entity section in Data Flow modeling, this step should be straightforward, albeit with a minor change.

Give the entity name as subtractor_circuit.

Next comes the circuit ports. The circuit has 2 inputs A and B. It is important to note that these inputs are not single valued inputs. They are vectors of size 4. Similarly, output F, is also a 4-bit vector.

Your entity should look as follows.

In A: in std_logic_vector(3 downto 0), the MSB of A is stored in A(3) and its LSB is stored in A(0).

This completes the entity.

Learn about the procedure to write the architecture here.