Verilog code for full subractor and testbench
Post date: Oct 22, 2017 8:17:06 AM
Test File
module fs(a, b, c, borrow, difference);
input a;
input b;
input c;
output borrow;
output different;
wire d,e,f;
xor(difference,a,b,c);
and(d,~a,b);
and(e,b,c);
and(f,~a,c);
or(borrow,d,e,f);
endmodule
Test Bench File
module fullsubt_b;
reg a;
reg b;
reg c;
wire borrow;
wire difference;
fs uut (.a(a), .b(b),.c(c),.borrow(borrow),.difference(difference) );
initial begin
#10 a=1’b0;b=1’b0;c=1’b0;
#10 a=1’b0;b=1’b0;c=1’b1;
#10 a=1’b0;b=1’b1;c=1’b0;
#10 a=1’b0;b=1’b1;c=1’b1;
#10 a=1’b1;b=1’b0;c=1’b0;
#10 a=1’b1;b=1’b0;c=1’b1;
#10 a=1’b1;b=1’b1;c=1’b0;
#10 a=1’b1;b=1’b1;c=1’b1;
#10$stop;
end