Decoder

Post date: Nov 22, 2017 7:14:38 AM

In both the multiplexer and the demultiplexer, part of the circuits decode the address inputs, i.e. it translates a binary number of n digits to 2ⁿoutputs, one of which (the one that corresponds to the value of the binary number) is 1 and the others of which are 0.

It is sometimes advantageous to separate this function from the rest of the circuit since it is useful in many other applications. Thus, we obtain a new combinatorial circuit that we call the decoder. It has the following truth table (for n = 3):

a2 a1 a0 | d7 d6 d5 d4 d3 d2 d1 d0 ---------------------------------- 0 0 0 | 0 0 0 0 0 0 0 1 0 0 1 | 0 0 0 0 0 0 1 0 0 1 0 | 0 0 0 0 0 1 0 0 0 1 1 | 0 0 0 0 1 0 0 0 1 0 0 | 0 0 0 1 0 0 0 0 1 0 1 | 0 0 1 0 0 0 0 0 1 1 0 | 0 1 0 0 0 0 0 0 1 1 1 | 1 0 0 0 0 0 0 0

Problem Description:

Consider the circuit diagram for full adder using a 3x8 decoder given below.

It takes 3-bit input number and produce Sum and Carry bit as an output

Equation

S(x, y, z) = ∑(1,2,4,7)

C(x,y, z) = ∑(3,5,6,7)

HDL Program for Decoder:-

[Decoder.v]

module decoder(d0,d1,d2,d3,d4,d5,d6,d7,x,y,z); input x,y,z; output d0,d1,d2,d3,d4,d5,d6,d7; wire x0,y0,z0; not n1(x0,x); not n2(y0,y); not n3(z0,z); and a0(d0,x0,y0,z0); and a1(d1,x0,y0,z); and a2(d2,x0,y,z0); and a3(d3,x0,y,z); and a4(d4,x,y0,z0); and a5(d5,x,y0,z); and a6(d6,x,y,z0); and a7(d7,x,y,z); endmodule

[DecoderFA.v]

module fadder(s,c,x,y,z); input x,y,z; wire d0,d1,d2,d3,d4,d5,d6,d7; output s,c; decoder dec(d0,d1,d2,d3,d4,d5,d6,d7,x,y,z); assign s= d1|d2|d4|d7, c=d3|d5|d6|d7; endmodule

Test Bench File

module testbench; reg x,y,z; wire s,c; FADDER fl(s,c,x,y,z); initial $monitor(,$time,"x=%b,y=%b,z=%b,s=%b,c=%b",x,y,z,s,c); initial begin #0 x=1'b0;y=1'b0;z=1'b0; #4 x=1'b1;y=1'b0;z=1'b0; #4 x=1'b0;y=1'b1;z=1'b0; #4 x=1'b1;y=1'b1;z=1'b0; #4 x=1'b0;y=1'b0;z=1'b1; #4 x=1'b1;y=1'b0;z=1'b1; #4 x=1'b0;y=1'b1;z=1'b1; #4 x=1'b1;y=1'b1;z=1'b1; end endmodule