VerilogPro - HDL (Hardware Description Language]

Verilog is a Hardware Description Language; a textual format for describing electronic circuits and systems. Applied to electronic design, Verilog is intended to be used for verification through simulation, for timing analysis, for test analysis (testability analysis and fault grading) and for logic synthesis.

T - Flip Flop — Nov 29, 2017 6:18:17 AM

D Flip Flop — Nov 29, 2017 6:13:13 AM

JK Flip Flop — Nov 29, 2017 6:05:29 AM

Sequential Circuit and Flip Flop — Nov 29, 2017 5:52:14 AM

D Flip Flop — Nov 28, 2017 6:21:58 AM

Decoder — Nov 22, 2017 7:14:38 AM

16 x 1 Multiplexer using 4 x 1 MUX — Nov 22, 2017 6:28:22 AM

4 to 1 Multiplexer and HDL Program — Nov 22, 2017 6:07:24 AM

HDL Program for 2-to-1 Multiplexer:- — Nov 1, 2017 6:55:29 AM

HDL Program to Simulate Simple Circuit — Oct 25, 2017 7:14:14 AM

HDL Program in Verilog Pro for AND Gate — Oct 25, 2017 7:10:01 AM

Verilog code for full subractor and testbench — Oct 22, 2017 8:17:06 AM