D Flip Flop

Post date: Nov 29, 2017 6:13:13 AM

Delay Flip Flop / D Flip Flop

Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter connected between S and R inputs. It has only one input. The input data is appearing at the output after some time. Due to this data delay between i/p and o/p, it is called delay flip-flop. S and R will be the complements of each other due to NAND inverter. Hence S = R = 0 or S = R = 1, these input condition will never appear. This problem is avoid by SR = 00 and SR = 1 conditions.

Block Diagram

Circuit Diagram

Truth Table

Verilog HDL Program

[dff.v]

module diff(Q,D,clk);

input clk,D;

output Q;

reg Q;

always @(posedge clk)

begin

Q<=D;

end

endmodule

Test Bench File [dff_testbench.v]

module diff_tb;

reg D,clk;

wire Q;

integer i;

diff diff_inst(Q,D,clk);

initial

begin

D=1'b0;clk=1'b1;

#20 D=1'b0;clk=~clk;

for(i=0;i<10;i=i+1)

begin

#40 clk=~clk;

D=D+1'b1;

end

endmodule