HDL Program in Verilog Pro for AND Gate

Post date: Oct 25, 2017 7:10:01 AM

Source Code:-

module andgate(a,b,y);

input a,b;

output y;

and G1(y,a,b);

endmodule

Test bench Code

module t_andgate;

wire y;

reg a,b;

andgate therkmishra(a,b,y);

initial

begin

a= 1'b0;

b= 1'b0;

#5

a=1'b0;

b=1'b1;

#5

a=1'b1;

b=1'b0;

#5

a=1'b1;

b=1'b1;

end

initial #100 $finish;

endmodule