T - Flip Flop

Post date: Nov 29, 2017 6:18:17 AM

Toggle Flip Flop / T Flip Flop

Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected together. It has only input denoted by T as shown in the Symbol Diagram. The symbol for positive edge triggered T flip flop is shown in the Block Diagram.

Symbol Diagram

Block Diagram

Truth Table

Operation

Verilog HDL Program for T Flip Flop

[tff.v]

module TFF(T,clk,rst,q);

input T,clk,rst;

output q;

reg q;

always@(posedge clk or negedge rst)

begin

if(~rst)

begin

q<=1'b0;

end

else if(T)

begin

q<=!q;

end

end

endmodule

[tff_testbench.v]

module TFF_tb;

reg T,clk,rst;

wire q;

TFF inst1(T,clk,rst,q);

initial

begin

T=1'b0; clk=1'b0; rst=1'b0;

#20 T=1'b1; clk=~clk;

#20 T=1'b0; clk=~clk;

#20 T=1'b1; clk=~clk; rst=~rst;

#20 T=1'b0; clk=~clk;

#20 T=1'b1; clk=~clk;

#20 T=1'b0; clk=~clk; rst=~rst;

#20 T=1'b1; clk=~clk;

#20 T=1'b0; clk=~clk;

#20 T=1'b1; clk=~clk; rst=~rst;

#20 T=1'b0; clk=~clk;

end

endmodule

Note:-

always Statement

All behavioral statements inside an always statement constitute an always block. The always statement starts at time 0 and executes the statements in the always block continuously in a looping fashion. This statement is used to model a block of activity that is repeated continuously in a digital circuit. An example is a clock generator module that toggles the clock signal every half cycle.

module clock_gen (output reg clock);

//Initialize clock at time zero

initial clock = 1'b0;

//Toggle clock every half-cycle (time period = 20)

always

#10 clock = ~clock;

initial

#1000 $finish;

endmodule