HDL Program to Simulate Simple Circuit

Post date: Oct 25, 2017 7:14:14 AM

Source File:-

module Simple_Circuit(A,B,C,D,E);

output D,E;

input A,B,C;

wire w1;

and G1(w1,A,B);

not G2(E,C);

or G3(D,w1,E);

endmodule

Test Bench

module t_Simple_Circuit_2;

wire w1,E,D;

reg A,B,C;

Simple_Circuit S1(A,B,C,D,E);

initial

begin

A=0;B=0;C=0;

#20

A=0;B=0;C=1;

#20

A=0;B=1;C=0;

#20

A=1;B=0;C=0;

#20

A=1;B=0;C=1;

#20

A=1;B=1;C=0;

#20

A=1;B=1;C=1;

#20

A=1;B=1;C=1;

#20

A=0;B=0;C=0;

end

initial #200 $finish;

endmodule