HDL Program for 2-to-1 Multiplexer:-

Post date: Nov 1, 2017 6:55:29 AM

2-to-1 Multiplexer

A multiplexer (or mux) is a common digital circuit used to mix a lot of signals into just one. If you want multiple sources of data to share a single, common data line, you’d use a multiplexer to run them into that line. Multiplexers come in all sorts of shapes and sizes, but they’re all made out of logic gates.

Every multiplexer has at least one select line, which is used to select which input signal gets relayed to the output. In a 2-to-1 multiplexer, there’s just one select line. More inputs means more select lines: a 4-to-1 multiplexer would have 2 select lines, an 8-to-1 has 3, and so on (2ⁿ inputs requires n select lines).

Think of a mux as a “digital switch”. The select line is the throw on the switch, it chooses which of the many inputs get to be the output.

Here’s how you might make a 2-to-1 multiplexer out of logic gates. A and B are the two inputs, X is the select input, and Y is the output.

Here’s what a truth table would look like for such a circuit:

//Behavior Description of Two-to-one-line Multiplexer

module Test(out,A,B,S);

input A,B,S;

output out;

wire n1,a1,a2;

not (n1,S);

and (a1,A,n1);

and (a2,B,S);

or(out,a1,a2);

endmodule

Test Bench File

module muxtest;

reg A,B,S;

wire out;

Test t2(out,A,B,S);

initial

begin

S=0; A=0;B=0;

#20

S=0;A=0;B=1;

#20

S=0;A=1;B=0;

#20

S=0;A=1;B=1;

#20

S=1;A=0;B=0;

#20

S=1;A=0;B=1;

#20

S=1;A=1;B=0;

#20

S=1;A=1;B=1;

#20

S=0;A=0;B=0;

end

initial

$monitor("A=%b B=%b S=%b out=%b time=%0d",

A,B,S,out,$time);

endmodule

===========================================================================================

2nd Method for MUX_2_to_1 Multiplexer

===========================================================================================

Description File

[Mux_2_to_1.v]

module mux(A,B,select,out);

input A,B,select;

output out;

assign out = select ?A:B;

endmodule

[Mux_2_to_1_Testbench.v]

module muxtest;

reg TA,TB,TS;

wire Y;

mux mx2X1(TA,TB,TS,Y);

initial

begin

TS=1;TA=0;TB=1;

#50 TA=0;TB=0;

#50 TS=0;

#50 TA=0;TB=1;

#50 TA=1;TB=0;

#50 TS=1;

#50 TA=1;TB=1;

#50 TA=0;TB=0;

end

initial

$monitor("select =%b A=%b B=%b out=%b time = %0d",TS,TA,TB,Y,$time);

endmodule

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1 AIM: DESIGN A 2X1 MUX USING CASE STATEMENT

module mux21(sel,d,q);

input sel;

input[1:0]d;

output q;

reg q;

always @(sel or d)

case(sel)

0: q=d[0];

1: q=d[1];

endcase

endmodule

module testmux;

reg tsel;

reg[1:0]td;

wire tq;

mux21 my(tsel,td,tq);

initial begin

tsel=0;td[1]=0;td[0]=0;

#50;tsel=0;td[1]=0;td[0]=1;

#50;tsel=0;td[1]=1;td[0]=0;

#50;tsel=0;td[1]=1;td[0]=1;

#50;tsel=1;td[1]=0;td[0]=0;

#50;tsel=1;td[1]=0;td[0]=1;

#50;tsel=1;td[1]=1;td[0]=0;

#50;tsel=1;td[1]=1;td[0]=1;

#50;

end initial

begin $monitor("time=%d sel=%d d[0]=%d d[1]=%d",$time,tsel,td[0],td[1],tq);

end

endmodule

2 AIM : DESIGN A 2X1 MUX USING LOGICAL EXPRESSION

module mux21(sel,d,q);

input sel;

input[1:0]d;

output q;

wire a,b,c;

assign a=~sel;

assign b=(a & d[0]);

assign c=(sel & d[1]);

assign q=(b+c);

endmodule

module testmux;

reg tsel;

reg[1:0]td;

wire tq;

mux21 my(tsel,td,tq);

initial begin

tsel=0;td[1]=0;td[0]=0;

#50;tsel=0;td[1]=0;td[0]=1;

#50;tsel=0;td[1]=1;td[0]=0;

#50;tsel=0;td[1]=1;td[0]=1;

#50;tsel=1;td[1]=0;td[0]=0;

#50;tsel=1;td[1]=0;td[0]=1;

#50;tsel=1;td[1]=1;td[0]=0;

#50;tsel=1;td[1]=1;td[0]=1;

#50;

end initial

begin $monitor("time=%d sel=%d d[0]=%d d[1]=%d",$time,tsel,td[0],td[1],tq);

end

endmodule

3 AIM: DESIGN A 2X1 MUX USING PRIMITIVE GATES

module mux21(sel,d,q);

input sel;

input[1:0]d;

output q;

wire a,b,c;

not n1(a,sel);

and(b,a,d[0]);

and(c,sel,d[1]);

or(q,b,c);

endmodule

module testmux;

reg tsel;

reg[1:0]td;

wire tq;

mux21 my(tsel,td,tq);

initial begin

tsel=0;td[1]=0;td[0]=0;

#50;tsel=0;td[1]=0;td[0]=1;

#50;tsel=0;td[1]=1;td[0]=0;

#50;tsel=0;td[1]=1;td[0]=1;

#50;tsel=1;td[1]=0;td[0]=0;

#50;tsel=1;td[1]=0;td[0]=1;

#50;tsel=1;td[1]=1;td[0]=0;

#50;tsel=1;td[1]=1;td[0]=1;

#50;

end initial

begin $monitor("time=%d sel=%d d[0]=%d d[1]=%d",$time,tsel,td[0],td[1],tq);

end

endmodule

4 AIM : DESIGN A 2X1 MUX USING IF ELSE

module mux21(sel,d,q);

input sel;

input[1:0]d;

output q;

reg q;

always @(sel or d)

begin

if(sel==0)

q=d[0];

else

q=d[1];

end

endmodule

module testmux;

reg tsel;

reg[1:0]td;

wire tq;

mux21 my(tsel,td,tq);

initial begin

tsel=0;td[1]=0;td[0]=0;

#50;tsel=0;td[1]=0;td[0]=1;

#50;tsel=0;td[1]=1;td[0]=0;

#50;tsel=0;td[1]=1;td[0]=1;

#50;tsel=1;td[1]=0;td[0]=0;

#50;tsel=1;td[1]=0;td[0]=1;

#50;tsel=1;td[1]=1;td[0]=0;

#50;tsel=1;td[1]=1;td[0]=1;

#50;

end initial

begin $monitor("time=%d sel=%d d[0]=%d d[1]=%d",$time,tsel,td[0],td[1],tq);

end

endmodule

5 AIM: DESIGN A 2X1 MUX USING CONDITIONAL OPERATOR

module mux21(sel,d,q);

input sel;

input[1:0]d;

output q;

assign q=(sel)?d[1]:d[0];

endmodule

module testmux;

reg tsel;

reg[1:0]td;

wire tq;

mux21 my(tsel,td,tq);

initial

begin

tsel=0;td[1]=0;td[0]=0;

#50;tsel=0;td[1]=0;td[0]=1;

#50;tsel=0;td[1]=1;td[0]=0;

#50;tsel=0;td[1]=1;td[0]=1;

#50;tsel=1;td[1]=0;td[0]=0;

#50;tsel=1;td[1]=0;td[0]=1;

#50;tsel=1;td[1]=1;td[0]=0;

#50;tsel=1;td[1]=1;td[0]=1;

#50;

end

initial

begin $monitor("time=%d sel=%d d[0]=%d d[1]=%d",$time,tsel,td[0],td[1],tq);

end

endmodule