Computer Architecture Lab
MIPS Architecture
The MIPS architecture is a Reduced Instruction Set Computer (RISC). This means that there is a smaller number of instructions, using a uniform instruction encoding format. Each instruction/operation does one thing (memory access, computation, conditional, etc.). The idea is to make the lesser number of instructions execute faster. In general RISC architectures, and specifically, the MIPS architecture, is designed for high-speed implementations.
Data Types/Sizes
Name Size
byte 8-bit integer
half 16-bit integer
word 32-bit integer
float 32-bit floating-point number
double 64-bit floating-point number
HDL Program for 2-to-1 Multiplexer — Nov 1, 2017 6:53:12 AM
MIPS Assembly Language using QtSpim — Oct 24, 2017 11:20:57 AM