JK Flip Flop

Verilog HDL Program for JK Flip Flop

[ jkflip.v ]

module jkflop(j,k,clk,rst,q);

input j,k,clk,rst;

output q;

reg q;

always @(posedge clk)

begin

if(j==1 & k==1 & rst==0)

begin

q <= ~q; //Toggles

end

else if(j==1 & k==0 & rst==0)

begin

q <= 1; //Set

end

else if(j==0 & k==1)

begin

q <= 0; //Cleared

end

else if(j==0 & k==0)

begin

q<=q; // no change

end

end

always @(posedge rst)

begin

q <= 0;

end

endmodule

Test Bench File [ jkfliptestbench.v]

module main;

reg j,k,clk,rst;

wire q;

jkflop jk(j,k,clk,rst,q);

//Module to generate clock with period 10 time units

initial

begin

clk=0;

repeat(30)

#10 clk=~clk;

end

initial

begin

j=0; k=0; rst=1;

#10

j=1; k=1; rst=0;

#10

j=0; k=1;rst=1;

#10

j=0; k=1;rst=0;

#10

j=1; k=0;rst=1;

#10

j=1; k=1;rst=0;

#10

j=0; k=0;

#10

j=1; k=0;

#10

j=0; k=1;rst=1;

end

endmodule