08日目～ランダム転送と期待値自動比較

class sample_scrbd_item extends uvm_object;

  bit [7:0] addr, data;

  `uvm_object_utils_begin(sample_scrbd_item)

    `uvm_field_int(addr, UVM_DEFAULT)

    `uvm_field_int(data, UVM_DEFAULT)

  `uvm_object_utils_end

  function new (string name="sample_scrbd_item");

    super.new(name);

  endfunction

endclass

`include "sample_seq_item.sv"

`include "sample_master_seq_lib.sv"

`include "sample_slave_seq_lib.sv"

`include "sample_scrbd_item.sv"

`include "sample_master_driver.sv"

`include "sample_master_monitor.sv"

`include "sample_master_sequencer.sv"

`include "sample_master_agent.sv"

`include "sample_slave_driver.sv"

`include "sample_slave_sequencer.sv"

`include "sample_slave_agent.sv"

`include "sample_env.sv"

class sample_master_monitor extends uvm_monitor;

  virtual sample_if vif;

  uvm_analysis_port #(sample_scrbd_item) ap_write;

  uvm_analysis_port #(sample_scrbd_item) ap_read;

  event scrbd_e;  //イベント定義

  `uvm_component_utils(sample_master_monitor)

  function new (string name, uvm_component parent);

    super.new(name, parent);

    ap_write = new("ap_write", this);

    ap_read  = new("ap_read", this);

  endfunction

  function void build_phase(uvm_phase phase);

    bit status;

    super.build_phase(phase);

    status = uvm_config_db#(virtual sample_if)::get(this, "", "vif", vif);

    if(status==1'b0)

      uvm_report_fatal("NOVIF", {"virtual interface must be set for: ",get_full_name(),".vif"});

  endfunction

  task run_phase(uvm_phase phase);

    string s_trans_kind;

    uvm_report_info("MONITOR", "Hi");

    fork scrbd_write; join_none  //スコアボード処理タスクを飛ばす

    forever begin

      @(posedge vif.valid);

      wait(vif.ready===1'b1);

      -> scrbd_e;    // イベント発行

      if(vif.write===1'b1)

        uvm_report_info("MON", $sformatf("write addr=%02xh wdata=%02xh", vif.addr, vif.wdata));

      else if(vif.write===1'b0)

        uvm_report_info("MON", $sformatf("read  addr=%02xh rdata=%02xh", vif.addr, vif.rdata));

      else

        uvm_report_info("MON", $sformatf("signal write is unknown..."));

    end

  endtask

  task scrbd_write;

    sample_scrbd_item item;

    forever begin

      @scrbd_e;

      item = new();

      item.addr = vif.addr;

      if(vif.write===1'b1)begin

        item.data = vif.wdata; // write側のanalysis_port

        ap_write.write(item);

      end else if(vif.write===1'b0)begin

        item.data = vif.rdata;

        ap_read.write(item);   // read側のanalysis_port

      end

    end

  endtask

endclass

class tb_env extends uvm_env;

  sample_env    sample_model;  //インスタンス名はenvでもいいが、もし複数のモデルを組み込むならば、個々に判別できる

                               //名前でなければならないため、このようなインスタンス名にしている

  gp_scoreboard #(sample_scrbd_item) sample_scrbd;  // 汎用スコアボード

  `uvm_component_utils(tb_env)

  function new (string name, uvm_component parent);

    super.new(name, parent);

  endfunction

  function void build_phase(uvm_phase phase);

    super.build_phase(phase);

    sample_model = sample_env::type_id::create("sample_model", this);

    sample_scrbd = gp_scoreboard#(sample_scrbd_item)::type_id::create("sample_scrbd", this);

  endfunction

  function void connect_phase(uvm_phase phase);

    sample_model.master.monitor.ap_write.connect(sample_scrbd.ap_exp); //期待値用

    sample_model.master.monitor.ap_read.connect(sample_scrbd.ap_obs);  //観測地用

  endfunction

endclass

`timescale 1ps/1ps

module tb_top;

  // UVM class library

  `include "uvm_macros.svh"

  import uvm_pkg::*;

  // common library

  `include "gp_scoreboard.sv"

  // uvm user code

  `include "sample_model.svh"

  `include "tb_env.sv"

  `include "sample_test.sv"

  /////////////////////////////////////

class sample_test extends uvm_test;

  `uvm_component_utils(sample_test)

  tb_env tb;

  function new (string name="sample_test", uvm_component parent=null);

    super.new(name,parent);

  endfunction

  function void build_phase(uvm_phase phase);

    super.build_phase(phase);

    uvm_config_db#(uvm_object_wrapper)::set(this,

        "tb.sample_model.master.sequencer.run_phase", "default_sequence",

        write_read_seq::type_id::get());

    uvm_config_db#(uvm_object_wrapper)::set(this,

        "tb.sample_model.slave.sequencer.run_phase", "default_sequence",

        normal_response_seq::type_id::get());

    tb = tb_env::type_id::create("tb", this);

  endfunction

  task run_phase(uvm_phase phase);

    uvm_report_info("TEST", "Hello World");

    uvm_top.print_topology();

  endtask

endclass

class write_read_all_seq extends sample_master_base_seq;

  write_seq _write;

  read_seq  _read;

  `uvm_object_utils(write_read_all_seq)

  function new (string name="write_read_all_seq");

    super.new(name);

  endfunction

  virtual task body();

    int i;

    for(i=0; i<256; i=i+1)begin

      `uvm_create(_write)

      _write.addr = i;

      _write.data = $urandom_range(255,0);

      `uvm_send(_write)

    end

    for(i=0; i<256; i=i+1)begin

      `uvm_create(_read)

      _read.addr = i;

      `uvm_send(_read)

    end

  endtask

endclass

他に、sample_slave_driver.svも修正してください。（これはバグ修正）

seq_item_port.item_done(req);  //reqを消してください

uvm_testクラスの追加ですが、このページの一番下を御覧ください。記述量削減したコードを掲載しています。

class write_read_rand_all_seq extends sample_master_base_seq;

  write_seq _write;

  read_seq  _read;

  `uvm_object_utils(write_read_rand_all_seq)

  function new (string name="write_read_rand_all_seq");

    super.new(name);

  endfunction

  virtual task body();

    int i, remain, len;

    bit [7:0] addr_q[$], read_addr_q[$];

    // アドレス生成

    for(i=0; i<256; i=i+1)begin

      addr_q.push_back(i);

    end

    while(addr_q.size() != 0)begin

      len = $urandom_range(16,1);  // 1-16のrandom値生成

      if( (addr_q.size()-len) < 0 ) len = remain;

      //remain = remain - len;

      $display("==================================================================");

      uvm_report_info("SEQ", $sformatf("Transaction Start. length=%0d", len));

      for(i=0; i<len; i=i+1)begin

        bit [7:0] addr;

        `uvm_create(_write)

        addr = gen_rand_addr(addr_q);

        read_addr_q.push_back(addr);

        _write.addr = addr;

        _write.data = $urandom_range(255,0);

        `uvm_send(_write)

      end

      $display("------------------------------------------------------------------");

      for(i=0; i<len; i=i+1)begin

        `uvm_create(_read)

        _read.addr = gen_rand_addr(read_addr_q);

        `uvm_send(_read)

      end

    end

  endtask

  function bit [7:0] gen_rand_addr(ref bit [7:0] addr_src_q[$]);

    int index;

    bit [7:0] rval;

    //$display("remain=%0d", addr_src_q.size());

    index = $urandom_range(addr_src_q.size()-1,0);

    rval = addr_src_q[index];

    addr_src_q.delete(index);

    return rval;

  endfunction

endclass

  task scrbd_write;

    sample_scrbd_item item;

    forever begin

      @scrbd_e;

      item = new();

      item.addr = vif.addr;

      if(vif.write===1'b1)begin

        item.data = vif.wdata; // write側のanalysis_port

        item.`_GP_SCOREBOARD_MODE2_MARK = vif.addr;

        ap_write.write(item);

      end else if(vif.write===1'b0)begin

        item.data = vif.rdata;

        item.`_GP_SCOREBOARD_MODE2_MARK = vif.addr;

        ap_read.write(item);   // read側のanalysis_port

      end

    end

  endtask

`define _GP_SCOREBOARD_MODE2_MARK mark

module tb_top;

class tb_env extends uvm_env;

  sample_env    sample_model;

  gp_scoreboard #(sample_scrbd_item, bit[7:0]) sample_scrbd;

  `uvm_component_utils(tb_env)

  function new (string name, uvm_component parent);

    super.new(name, parent);

  endfunction

  function void build_phase(uvm_phase phase);

    super.build_phase(phase);

    uvm_config_db#(int)::set(this, "sample_scrbd", "mode", 2);

    sample_model = sample_env::type_id::create("sample_model", this);

    sample_scrbd = gp_scoreboard#(sample_scrbd_item, bit[7:0])::type_id::create("sample_scrbd", this);

  endfunction

  function void connect_phase(uvm_phase phase);

    sample_model.master.monitor.ap_write.connect(sample_scrbd.ap_exp); //期待値用

    sample_model.master.monitor.ap_read.connect(sample_scrbd.ap_obs);  //観測地用

  endfunction

endclass

class sample_scrbd_item extends uvm_object;

  bit [7:0] `_GP_SCOREBOARD_MODE2_MARK;

  bit [7:0] addr, data;

  `uvm_object_utils_begin(sample_scrbd_item)

    `uvm_field_int(addr, UVM_DEFAULT)

    `uvm_field_int(data, UVM_DEFAULT)

  `uvm_object_utils_end

  function new (string name="sample_scrbd_item");

    super.new(name);

  endfunction

endclass

`define set_seq(INST,SEQ) \

  uvm_config_db#(uvm_object_wrapper)::set(this,`"INST`","default_sequence",SEQ::type_id::get());

`define uvm_test_head(NAME) \

  class NAME extends sample_test_base; \

    `uvm_component_utils(NAME) \

    function new (string name=`"NAME`", uvm_component parent=null); \

      super.new(name,parent); \

    endfunction

//-------------------------------------------------------------

virtual class sample_test_base extends uvm_test;

  `uvm_component_utils(sample_test_base)

  tb_env tb;

  function new (string name="sample_test_base", uvm_component parent=null);

    super.new(name,parent);

  endfunction

  function void build_phase(uvm_phase phase);

    super.build_phase(phase);

    tb = tb_env::type_id::create("tb", this);

  endfunction

  task run_phase(uvm_phase phase);

    uvm_report_info("TEST", "Hello World");

    uvm_top.print_topology();

  endtask

endclass

//-------------------------------------------------------------

`uvm_test_head(sample_test)

  function void build_phase(uvm_phase phase);

    `set_seq(tb.sample_model.master.sequencer.run_phase, write_read_seq)

    `set_seq(tb.sample_model.slave.sequencer.run_phase,  normal_response_seq)

    super.build_phase(phase);

  endfunction

endclass

//-------------------------------------------------------------

`uvm_test_head(sample_test2)

  function void build_phase(uvm_phase phase);

    `set_seq(tb.sample_model.master.sequencer.run_phase, write_read_seq)

    `set_seq(tb.sample_model.slave.sequencer.run_phase,  random_response_seq)

    super.build_phase(phase);

  endfunction

endclass

//-------------------------------------------------------------

`uvm_test_head(sample_test3)

  function void build_phase(uvm_phase phase);

    `set_seq(tb.sample_model.master.sequencer.run_phase, write_read_all_seq)

    `set_seq(tb.sample_model.slave.sequencer.run_phase,  random_response_seq)

    super.build_phase(phase);

  endfunction

endclass

//-------------------------------------------------------------

`uvm_test_head(sample_test4)

  function void build_phase(uvm_phase phase);

    `set_seq(tb.sample_model.master.sequencer.run_phase, write_read_rand_all_seq)

    `set_seq(tb.sample_model.slave.sequencer.run_phase,  random_response_seq)

    super.build_phase(phase);

  endfunction

endclass