Novel Data Management Ideas on Heterogeneous Hardware Architectures (NoDMC)
Dirk Habich, TU Dresden  |  David Broneske, DZHW Hannover

The objective of this one-day workshop is to explore the challenges and opportunities of data processing on existing and future heterogeneous hardware architectures. On the one hand, today’s processors are no longer mainly bound by the density and frequency of transistors, but by their power and heat budgets. The so-called "power wall" forces hardware suppliers to rely more on the design of specialized devices optimized for certain types of calculations, which results in an increasingly heterogeneous processor landscape. On the other hand, memory and storage has seen an unprecedented change as well: novel and already commercially available techniques have blurred the traditional mental picture of a memory/storage hierarchy. For example, Non-Volatile RAM (NVRAM) is a prominent example to question the long-standing memory hierarchy reflected in almost all system-level applications. Moreover, very large caches, High-Bandwidth-Memory (HBM), Non-Uniform Memory Access (NUMA), or even remote-memory designs as well as extremely fast SSDs add to the heterogeneous portfolio of available memory/storage techniques. Therefore, to meet the performance requirements of the modern information society, tomorrow’s database systems will have to exploit and embrace this increased heterogeneity of processor and memory technologies.

The purpose of this workshop is to assist with training and fostering a community of researchers and industry practitioners working on data processing issues on heterogeneous hardware systems. To this end, we want to provide a forum to discuss challenges, progress and directions, and to offer an environment for networking persons researching on related topics and fostering future collaborations. Especially in the view of the SPP 2037 on Scalable Data Management for Future Hardware and the SPP 2377 on Disruptive Memory Technologies, we want to strengthen collaborations beyond individual SPP projects by connecting them with other researchers. This workshop welcomes research papers describing preliminary and ongoing research results (maximum length of 20 pages). In addition, we encourage the submission of visionary, new ideas and industry experiences on data processing on modern hardware architectures as extended abstracts of maximum 10 pages. Moreover, – related to the topics of this workshop – already published papers at international high-rank conferences or journals can be proposed for presentation with an extended abstract of maximum 4 pages. This workshop is co-organized by the GI-Arbeitskreis Data Management on Modern Hardware.

09:00 - 09:05 Welcome  

09:05 - 10:00 Keynote by David F. Bacon (Google Research)

10:30 - 12:30   Session 1 

•  W-4  1   [↗PDF] Accelerating Large Table Scan using Processing-In-Memory Technology (Baumstark, Alexander; Jibril, Muhammad Attahir; Sattler, Kai-Uwe)

•  W-4  2   [↗PDF] DNAContainer: An object-based storage architecture on DNA (El-Shaikh, Alex; Seeger, Bernhard)

•  W-4  3   [↗PDF] Benchmarking the Second Generation of Intel SGX for Machine Learning Workloads (Lutsch, Adrian; Singh, Gagandeep; Mundt, Martin; Mogk, Ragnar; Binnig, Carsten) 

•  W-4  4   [↗PDF] What We Can Learn from Persistent Memory for CXL (Benson, Lawrence;Weisgut, Marcel; Rabl, Tilmann) 

•  W-4  5   [↗PDF] Working with Disaggregated Systems. What are the Challenges and Opportunities of RDMA and CXL? (Geyer, Andreas; Ritter, Daniel; Lee, Dong Hun; Ahn, Minseon; Pietrzyk, Johannes; Krause, Alexander; Habich, Dirk; Lehner, Wolfgang)  

13:30 - 15:00   Session 2

•  W-4  5   [↗PDF] Enabling Integrated Data Analysis Pipelines on Heterogeneous Hardware through Holistic Extensibility (Extended Abstract on Novel Ideas) (Damme, Patrick; Boehm, Matthias) 

•  W-4  6   [↗PDF] An FPGA Avro Parser Generator for Accelerated Data Stream Processing (Hahn, Tobias; Schüll, Daniel; Wildermann, Stefan; Teich, Jürgen) 

•  W-4  7   [↗PDF] Inter-Query Parallelism on Heterogeneous Multi-Core CPUs (Schuhknecht, Felix Martin; Islam, Tamjidul) 

•  W-4  8   [↗PDF] Improving GPU Matrix Multiplication by Leveraging Bit Level Granularity and Compression (Fett, Johannes; Schwarz, Christian; Kober, Urs; Habich, Dirk; Lehner, Wolfgang)