The advancement of Integrated Circuit (IC) design technology has enabled the implementation of computationally complex processing algorithms for various biomedical and IoT applications with real-time and ultra-low-power operations. These interdisciplinary fields have the potential to significantly improve the quality of life by offering new approaches to diagnose and treat diseases and study the human body and brain.
A typical biomedical and IoT system comprises digital, analog, mixed-signal, and RF components, where ultra-low-power operation is a crucial aspect. As a researcher, my focus is on the development of such systems, particularly on a new class of hardware accelerators for neural implants that satisfy ultra-low-power and real-time operation requirements.
From a system perspective, two primary devices that consume a significant amount of power are memory, due to its essential role in performing digital signal processing algorithms, and intensive computational engine. To achieve ultra-low-power design, it is necessary to investigate memory usage and explore methods to improve power and area without compromising operating frequency and output accuracy.
Additionally, algorithms should be studied precisely to identify opportunities for applying different architectural techniques to reduce complexity, area, and power.
Programmability and flexibility are also crucial features for smart implants and IoT devices that require closed-loop system operation with minimal human interference. To achieve this, light and ultra-low-power CPUs play a pivotal role where energy efficiency remains a critical factor.
Here is a list of the projects initiated since April 2023:
[P16, Now] Neuralace ASIC at Blackrock Neurotech
[P15, 2023-2024] W_ICONs Neural Implant ASIC at Blackrock Neurotech
[P14, ongoing] Implementation of ASIC Design Flow at Blackrock Neurotech
[P13] Drafting Research Paper and Proposal at the University of Utah
Below is a chronologically ordered list of IC design projects completed at the Technical University of Dresden from 2012 to April 2023:
[P12, testing] PhD Chip (iceberg), to be updated soon.
[P11, under review] SYNC Chip, to be updated soon.
[P10] Ultra-Low-Power IoT device for Audio Processing (Scale4Edge Project, ORCA Chip)
[P8] 64-Channel data-aware Neural Recording and Stimulating Chip (Lotus Chip)
[P7] A 16-Channel Fully Configurable Smart Neural SoC (Gepard Chip)
[P6] Real-time Hardware Implementation of ARM Coresight Trace Decoder and Analyzer
[P3] Power and Area Efficient Ultra-Low Voltage Laplacian Pyramid Processing Engine
[P1] Structuring of Contourlet Transform for Pipeline-Based Implementation
Here is the list of Student Projects and studienarbeit (SP), paid projects (SHK), and the master thesis (MT) (co)supervised by me at TU Dresden (HPSN at TUD):
Master Thesis (MT)
[MT3] SW/HW implementation of multi-channel compression of neural signals (2022).
The modified version was taped out in the project [P11].
[MT2] Neural Signal Compression Hardware for A Real-time Multi-channel Brain Recording System (2019).
The modified version was taped out in the project [P8].
[MT1] Hardware acceleration of classification methods for a real-time multi-channel brain recording system (2019).
Student Projects and studienarbeit (SP)
[SP4] SW/HW Implementation of Arithmetic Coding for Neural Signal Compression (2022).
The modified version was taped out in the project [P11].
[SP3] Parallel and Serial Hardware Architecture of Neural Classifier with the parameterized RTL implementation (2022-2023).
The result was accepted/presented at IEEE BIOCAS 2022.
[SP2] SW/HW implementation of adaptive Golomb coding optimized for neural signal compression (2020).
The result was accepted/presented at IEEE BIOCAS 2021.
[SP1] Programming/completing MATLAB GUI interface for spike sorting project (2020).
Paid projects (SHK)
[SHK4] HW Implementation of a Packet-based Wrapper for Multi-channel Compression Engines (2022)
[SHK3] Extracellular dataset collection/developing software interface/documentation (2021).
[SHK2] Comparison and documentation of existing open-source RISC-V hardware implementations and the software flow (2021).
[SHK1] Various neural signals feature extraction (2020).
Here is the list of the digital design projects, done before 2012:
Initiating the TMS320c50 training board, 2010.
Design and implementation of Dust3964 to RS232 interface and vice versa, 2009.
Intelligent power-on and regulatory circuit of security systems, 2007.
Switching power supply digital controller, 2007.
AVR and MCS-51Training Kit, 2007.
Design an ISA interface card, 2006.
Digital design of six space vector PWM controller, 2006.