Project Description:

Multielectrode intracranial recording technology provides high spatial and temporal resolution, making it an essential tool for neural prosthetic development and neuroscience research. To analyze recorded brain signals, spike sorting is used to identify their source neurons. This process is critical for various applications, including brain-machine interfaces (BMI) and neural prostheses, where ultra-low power consumption is necessary.

In this project, I proposed a power- and area-efficient spike sorting processor (SSP) for real-time neural recordings. Our SSP includes novel algorithms for detection, feature extraction, and improved K-means clustering for higher accuracy and better online performance, while also reducing power and area per channel. To reduce dynamic power, I used time-multiplexed registers in the detector. Additionally, we develop an ultra-low voltage 8T static random access memory (SRAM) that uses less area and consumes less leakage power than D flip-flop-based memory.

The chip consumes only 0.175 µW/channel while processing 128 input channels at 3.2 MHz and 0.54 V, making it the lowest power consumption among compared state-of-the-art SSPs. It also occupies only 0.003 mm2/channel, allowing for 333 channels/mm2. Our 

This project won the Student Design Contest Award at ISLPED(2016) and Best Live Demonstration Award at APCCAS(2016).

Hardware Implementation:

• Fabricated in 65-nm CMOS process technology.

Please refer to the following publications for further details:

• [J4] A. Do, S. M. A. Zeinolabedin, D. Jeon, D. Sylvester, and T. Kim, "An Area Efficient 128-Channel Spike Sorting Processor for Real-time Neural Recording with 0.175 µW per Channel in 65-nm CMOS," IEEE Transactions on VLSI Systems (TVLSI), 2019.(link) 

• [C8] S. M. A. Zeinolabedin, A. T. Do, D. Jeon, D. Sylvester, and T. Kim, "A 128-Channel Spike Sorting Processor Featuring 0.175 µW and 0.0033 mm2 per Channel in 65-nm CMOS,"Symposium on VLSI Circuits (VLSIC), June 2016.(link)

• [C6] S. M. A. Zeinolabedin, A. Do, K.-S. Yeo, and T. Kim, "Design of a Hybrid Neural Spike Detection Algorithm for Implantable Integrated Brain Circuits," IEEE International Symposium on Circuits and Systems (ISCAS), May 2015.(link)