Journal papers:
[J11] A. Rostami, S. M. A. Zeinolabedin, L. Guo, F. Kelber, H. Bauer, A. Dixius, S. Scholze, M. Berthel, D. Walter, J. Uhlig, B. Vogginger, C. Mayr, "NLU: An Adaptive, Small-Footprint, Low-Power Neural Learning Unit for Edge and IoT Applications ", IEEE Open Journal of Circuits and Systems (OJCS), 2025
[J10] L. Guo, A. Weiße, S. M. A. Zeinolabedin, F. M. Schüffny, M. Stolba, Q. Ma, Z. Wang, S. Scholze, A. Dixius, M. Berthel, J. Partzsch, D. Walter, G. Ellguth, S. Hoppner, R. George, and Christian Mayr, “68-Channel Highly-Integrated Neural Signal Processing PSoC with On-Chip Feature Extraction, Compression, and Hardware Accelerators for Neuroprosthetics in 22nm FDSOI,” Frontiers in Neuroscience, 2024.
[J9] F. Schüffny, S. Hoeppner, S. Hanzsche, R. George, S. M. A. Zeinolabedin, and C. Mayr, “Power Minimisation in Neural Recording ΔΣ Modulators by Adaptive Back-Gate Voltage Tuning,” IEEE Solid-State Circuits Letters (SSC-L), 2023.
[J8] S. M. A. Zeinolabedin, F. M. Schuffny, R. George, F. Kelber, H. Bauer, S. Scholze, S. Hänzsche, M. Stolba, A. Dixius, G. Ellguth, D. Walter, S. Höppner and C. Mayr. A 16-Channel Fully Configurable Neural SoC with 1.52μW⁄Ch Signal Acquisition, 2.79μW⁄Ch Real-time Spike Classifier, and 1.79 TOPS⁄W Deep Neural Network Accelerator in 22nm FDSOI. IEEE Transactions on Biomedical Circuits and Systems (TBIOCAS), 2022.
[J7] F. Schüffny, S. Höppner, S. Hänzsche, R. Miru George, S. M. A. Zeinolabedin, and C. Mayr, "An Ultra-Low Area Digital-Assisted Neuro Recording System in 22nm FDSOI Technology," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), 2021.
[J6] S. M. A. Zeinolabedin, J. Partzsch, and C. Mayr, “Real-time Hardware Implementation of ARM CoreSight Trace Decoder,” IEEE Design & Test (IDT), 2021.
[J5] A. Do, S. M. A. Zeinolabedin, and T. Kim, "Energy-Efficient Data-Aware SRAM Design Utilizing Column-based Data Encoding," IEEE Transactions on Circuits and Systems II (TCAS-II), 2020.
[J4] A. Do, S. M. A. Zeinolabedin, D. Jeon, D. Sylvester, and T. Kim, "An Area Efficient 128-Channel Spike Sorting Processor for Real-time Neural Recording with 0.175 µW per Channel in 65-nm CMOS," IEEE Transactions on VLSI Systems (TVLSI), 2019.
[J3] S. M. A. Zeinolabedin, J. Zhou, X. Liu, and T. Kim, " A Power and Area Efficient Ultra-low Voltage Laplacian Pyramid Processing Engine with Adaptive Data Compression,” IEEE Transactions on Circuits and Systems-I (TCAS-I), 2016.
[J2] S. M. A. Zeinolabedin, J. Zhou, X. Liu, and T. Kim, "An Area and Energy Efficient FIFO Design using Error-Reduced Data Compression and Near-threshold Operation for Image/Video Applications," IEEE Transactions on VLSI Systems (TVLSI), 2015.
[J1] S. M. A. Zeinolabedin, N. Karimi, S. Samavi, and T. Kim, "Structuring of Contourlet Transform for Pipeline-based Implementation," Circuits, Systems & Signal Processing (CSSP), pp. 1-24, 2015.
Conference papers:
[C20] S. M. A. Zeinolabedin, M. Couriol, P-E. Gaillard, “Selecting IRN for AFE to Achieve Power-Area-Noise Efficiency in Next-Generation Neural Implants”, IEEE International Midwest Symposium on Circuits and Systems (MWCAS), August 2024.
[C19] L. Guo, M. Jobst, J. Partzsch, S. Scholze, A. Dixius, M. Lohrmann, S. M. A. Zeinolabedin, C. Mayr, "A Low-Power Memory-Efficient Hardware Accelerator of MFCC Extraction for Keyword Spotting in 22nm FDSOI”, IEEE 5th International Conference on Artificial Intelligence Circuits & Systems (AICAS), June 2023.
[C18] F. M. Schüffny, S. Hanzsche, S. Henker, S. M. A. Zeinolabedin, S. Scholze, S. Hoppner, R. M. George, C. Mayr, "A 3.3V Saturation-Aware Neurostimulator with Reset Functionality in 22nm FDSOI”, IEEE Interregional NEWCAS Conference, May 2023.
[C17] L. Guo, S. M. A. Zeinolabedin, F. M. Schüffny, A. Weiße,S. Scholze, R. M. George, J. Partzsch, Christian Mayr, “A 16-channel Real-time Adaptive Neural Signal Compression Engine in 22nm FDSOI”, IEEE Interregional NEWCAS Conference, May 2023.
[C16] F. M. Schuffny, S. Hanzsche, M. Berthel, S. M. A. Zeinolabedin, S. Scholze, S. Hoppner, R. M. George, C. Mayr, “A Single Battery Supply Power Concept for a Neuro Recording and Flexible Processing Chain in 22 nm”, IEEE Nordic Circuits and Systems Conference (NorCAS), 2022.
[C15] S. Guo, L. Guo, S. M. A. Zeinolabedin, Christian Mayr, “Various Distance Metrics Evaluation on Neural Spike Classification”, IEEE Biomedical Circuits and Systems Conference (BIOCAS), 2022.
[C14] F. M. Schüffny, S. M. A. Zeinolabedin, R. George, L. Guo, A. Weiße, J. Uhlig, J. Meyer, A. Dixius, S. Hänzsche, M. Berthel, S. Scholze, S. Höppner, C. Mayr, "A 64-Channel back-Gate Adapted ultra-low-Voltage spike- Aware Neural Recording front-End with on-Chip lossless/near-Lossless Compression Engine and 3.3V Stimulator in 22nm FDSOI", IEEE Asian Solid-State Circuits Conference (ASSCC), 2022.
[C13] F. M. Schüffny, S. Höppner, S. M. A. Zeinolabedin, R. M. George and C. Mayr, "How to design an input stage for neural recording system in 22 nm FDSOI", IEEE 17th International Conference on PhD Research in Microelectronics and Electronics (PRIME), 2022.
[C12] Q. Ma, L. Guo, S. M. A. Zeinolabedin, and C. Mayr, "Ultra-low Power and Area-efficient Hardware Accelerator for Adaptive Neural Signal Compression," IEEE Biomedical Circuits and Systems Conference (BIOCAS), 2021.
[C11] S. M. A. Zeinolabedin, J. Partzsch, and C. Mayr, “Analyzing ARM CoreSight ETMv4.x Data Trace Stream with a Real-time Hardware Accelerator,” Design, Automation and Test in Europe Conference (DATE), 2021.
[C10] S. M. A. Zeinolabedin, F. M. Schüffny, J. Partzsch, R. George, A. Weiße, C. Mayr, “Design Challenges of Real-time Hardware Implementation of Seizure Prediction Chip,” International Conference for Technology and Analysis of Seizures (ICTALS), 2019.
[C9] A. T. Do, S. M. A. Zeinolabedin and T. Kim, "A 0.3 pW/Access 8T Data-Aware SRAM Utilizing Column-based Data Encoding for Ultra-Low Power Applications," IEEE Asian Solid State Circuits Conference (ASSCC), Nov. 2016.
[C8] S. M. A. Zeinolabedin, A. T. Do, D. Jeon, D. Sylvester, and T. Kim, "A 128-Channel Spike Sorting Processor Featuring 0.175 µW and 0.0033 mm2 per Channel in 65-nm CMOS,"Symposium on VLSI Circuits (SOVC), June 2016.
[C7] S. M. A. Zeinolabedin, J. Zhou, X. Liu, and T. Kim, "A 0.5V Power and Area Efficient Laplacian Pyramid Processing Engine using FIFO with Adaptive Data Compression," IEEE European Solid-State Circuits Conference (ESSCIRC), Sept. 2015.
[C6] S. M. A. Zeinolabedin, A. Do, K.-S. Yeo, and T. Kim, "Design of a Hybrid Neural Spike Detection Algorithm for Implantable Integrated Brain Circuits," IEEE International Symposium on Circuits and Systems (ISCAS), May 2015.
[C5] S. M. A. Zeinolabedin, Jun Zhou, Xin Liu and Tony T. Kim, “An Area- and Power-Efficient FIFO with Error-Reduced Data Compression for Image/Video Processing”, IEEE International Symposium on Circuits and Systems (ISCAS), June 2014.
[C4] S. M. A. Zeinolabedin, N. Karimi, “A New Quantization Algorithm for FIR Filters Coefficients”, IEEE 20th Iranian Conference on Electrical Engineering (ICEE), 2012.
[C3] I. Kianpour, M. Baghaei-Nejad, S. M. A. Zeinolabedin and Li-Rong Zheng, “A Subthreshold Ultra Low Power 22fJ/conversion Flash ADC for RFID Sensing Applications”, IEEE 19th Iranian Conference On Electrical Engineering (ICEE), 2011.
[C2] S. M. A. Zeinolabedin, N. Karimi, S. Samavi, “Low Computational Complexity Hardware Implementation of Laplacian Pyramid”, IEEE 18th Iranian Conference on Electrical Engineering (ICEE), 2010.
[C1] N. Karimi, S. Samavi, S. Shirani, H. Talebi, S. M. A Zaynolabedin, "Contourlet based image compression using controlled modification of coefficients", Canadian Conference on Electrical and Computer Engineering, 2009
Awards:
[D4] 2016 APCCAS Best Live Demonstration Award.
[D3] 2016 ISLPED Student Design Contest Award.
[D2] 2014 ISCAS Student Travel Award.
[D1] 2012-2016 Singapore International Graduate Award (SINAG) Scholarship.
Journal Reviewer for:
IEEE Transactions on VLSI Systems (TVLSI)
IEEE Transactions on Biomedical Circuits and Systems (TBioCAS)
IEEE Transactions on Circuits and Systems I (TCAS-I)