[P2] Area and Energy Efficient FIFO Design
[P2] Area and Energy Efficient FIFO Design
Project Description:
While several methods have been developed to minimize power consumption in FIFOs, most focus on circuit-level techniques and memory-splitting schemes, along with power gating. In this project, I propose a novel approach: a FIFO architecture with adaptive error-reduced data compression (FAERDC) and a FIFO with error-reduced data compression (FERDC) to reduce FIFO size with negligible degradation in error metrics like mean square error (MSE) and peak signal-to-noise ratio (PSNR). The proposed method not only reduces the FIFO size but also improves dynamic and leakage power consumption.
Experimental results show that the proposed FIFO, operating at 0.5V and 28.57MHz, achieves a reduction of up to 99%, 65%, and 34.91% in dynamic power, leakage power, and area, respectively, with a small MSE of 2.76 compared to the conventional FIFO design.
Hardware Implementation:
Post-synthesis implementation and simulation using a 0.18-µm CMOS process technology.
Please refer to the following publications for further details:
[J2] S. M. A. Zeinolabedin, J. Zhou, X. Liu, and T. Kim, "An Area and Energy Efficient FIFO Design using Error-Reduced Data Compression and Near-threshold Operation for Image/Video Applications," IEEE Transactions on VLSI Systems (TVLSI), 2015.(link)
[C5] S. M. A. Zeinolabedin, Jun Zhou, Xin Liu and Tony T. Kim, “An Area- and Power-Efficient FIFO with Error-Reduced Data Compression for Image/Video Processing”, IEEE International Symposium on Circuits and Systems (ISCAS), June 2014.(link)