Project Description:

The Laplacian Pyramid (LP) is a popular multi-resolution image representation technique in image and video processing applications, such as image fusion, compression, feature extraction, and object recognition. However, existing hardware implementations of LP primarily focus on performance, rather than power consumption. With portable applications becoming increasingly popular, the demand for system miniaturization and low power consumption is growing, shifting the design focus from performance to area and power optimization.

To address this issue, we propose the LP processing engine (LPPE) chip, aimed at optimizing power and area. The LPPE consumes only 452 μW/frame, with a clock frequency of 3.68 MHz and 112 frames per second, at 0.5 V. Compared to the conventional counterpart, the proposed LPPE achieves an area reduction of 18.98%-36.06%.

Hardware Implementation:

• Fabricated at a 0.18 µm CMOS process technology. 

• Described in VHDL and then synthesized using the Cadence RTL Compiler.

• PnR was done by the Cadence SOC Encounter applying the CPF (common power format) flow for the low power design. 

• A Xilinx ZYNQ-7000 SOC video and imaging kit with Xilinx FMC XM105 debug cards was used to test the chip.

Please refer to the following publications for further details:

• [J3] S. M. A. Zeinolabedin, J. Zhou, X. Liu, and T. Kim, " A Power and Area Efficient Ultra-low Voltage Laplacian Pyramid Processing Engine with Adaptive Data Compression” IEEE Transactions on Circuits and Systems-I (TCAS-I), 2016.(link)

• [C7] S. M. A. Zeinolabedin, J. Zhou, X. Liu, and T. Kim, "A 0.5V Power and Area Efficient Laplacian Pyramid Processing Engine using FIFO with Adaptive Data Compression," IEEE European Solid-State Circuits Conference (ESSCIRC), Sept. 2015.(link)

• [C2] S. M. A. Zeinolabedin, N. Karimi, S. Samavi, “Low Computational Complexity  Hardware  Implementation of Laplacian Pyramid”, IEEE 18th Iranian Conference on Electrical Engineering (ICEE), 2010.(link)