[P6] Real-time Hardware Implementation of ARM Coresight Trace Decoder and Analyzer
[P6] Real-time Hardware Implementation of ARM Coresight Trace Decoder and Analyzer
Project Description:
Modern SoC design faces significant challenges in debugging and verification due to the inclusion of multiple processing engines, different peripherals, and network-on-chip hierarchies. Debugging techniques play a critical role in the development and operation of multicore SoCs. The current approach involves recording debugging information and offline processing it, which produces a compressed trace with detailed debug information. However, the SoC internal buffer has limitations, and the recording trace is restricted to a short-time window, whereas debugging and verification require arbitrary time to analyze and test the system.
To address these issues, this project proposes a new approach that realizes the debug platform consisting of "trace decoder" and "monitoring" in hardware to achieve real-time performance.
Hardware Implementation:
Implemented on Xilinx Virtex xc6vcx75t-2ff784 FPGA device.
Please refer to the following publications for further details:
[C11] S. M. A. Zeinolabedin, J. Partzsch, and C. Mayr, “Analyzing ARM CoreSight ETMv4.x Data Trace Stream with a Real-time Hardware Accelerator,” Design, Automation and Test in Europe Conference, 2021.(link)
[J6] S. M. A. Zeinolabedin, J. Partzsch, and C. Mayr, “Real-time Hardware Implementation of ARM CoreSight Trace Decoder,”, IEEE Design Test, 2021.(link)