Project Description:

Besides being the technical coordinator for the project during the tape-out phase, I was responsible for overseeing the setup and execution of regression and coverage for the top-level design. Additionally, I played a key role in facilitating technical meetings between designers and monitoring the design's progress to ensure the project met its tape-out deadline.

Hardware Implementation:

• Fabricated in 22-nm FDSOI SoC technology.

Please refer to the following publications for further details:

• [C19] L. Guo, M. Jobst, J. Partzsch, S. Scholze, A. Dixius, M. Lohrmann, S. M. A. Zeinolabedin, C. Mayr, "A Low-Power Memory-Efficient Hardware Accelerator of MFCC Extraction for Keyword Spotting in 22nm FDSOI”, IEEE 5th International Conference on Artificial Intelligence Circuits & Systems (AICAS), June 2023.