Project Description:

In this project, we present a fully configurable neural SoC integrating the following components: 

• 16-channel analog front end (AFE) containing 16 LNAs time-multiplexed to a chopped VGA and 9 bit SAR ADC. Digital assisted filtering makes the AFE more robust with respect to PVT-variation. 

• On-chip CPU providing the programmability feature to perform various training/evaluation algorithms in power efficient modes.

• Dedicated bio-processing accelerators running detection and classification independent of the CPU to achieve ultra-low-power performance. 

• 16x4 multiply accumulate (MAC) array providing 8-bit unsigned acceleration of time-critical matrix multiplications or 2D (dimensional) convolution 

The proposed system achieves an average classification accuracy of 94.12% and power consumption of 2.79 µW/Ch for the classification and 1.52 µW/Ch for the AFE. Various architecture- and circuit-level techniques are deployed to achieve the ultra-low-power operation. 

Hardware Implementation:

• Fabricated in 22-nm FDSOI SoC technology.

Please refer to the following publications for further details:

• [J8] S. M. A. Zeinolabedin, F. M. Schuffny, R. George, F. Kelber, H. Bauer, S. Scholze, S. Hänzsche, M. Stolba, A. Dixius, G. Ellguth, D. Walter, S. Höppner and C. Mayr. A 16-Channel Fully Configurable Neural SoC with 1.52μW⁄Ch Signal Acquisition, 2.79μW⁄Ch Real-time Spike Classifier, and 1.79 TOPS⁄W Deep Neural Network Accelerator in 22nm FDSOI. IEEE Transactions on Biomedical Circuits and Systems (TBIOCAS), 2022. (link)

• [J7] F. Schüffny, S. Höppner, S. Hänzsche, R. Miru George, S. M. A. Zeinolabedin, and C. Mayr, "An Ultra-Low Area Digital-Assisted Neuro Recording System in 22nm FDSOI Technology," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), 2021. (link)

• [C13]  F. M. Schüffny, S. Höppner, S. M. A. Zeinolabedin, R. M. George and C. Mayr, "How to design an input stage for neural recording system in 22 nm FDSOI", IEEE 17th International Conference on PhD Research in Microelectronics and Electronics (PRIME), 2022.