Project Description:

In this project, we proposed an 8T SRAM with a column-based data encoding scheme aimed at reducing read and write power consumption when consecutive data have similarities. This is especially useful in image processing applications where neighboring pixels tend to have similar values. To compensate for the read-bitline leakage during ultra-low voltage operation, we employed a PVT-tracking reference voltage generator.

The proposed design offers more than 30% reduction in WBL switching power on average. We implemented a 32Kb SRAM using a 65 nm CMOS process, and it demonstrated successful operation down to 0.36 V. At a maximum frequency of 0.25 MHz, the total power consumption is 0.37 µW, and the minimum energy is achieved at 0.5 V with 0.3 pJ/access.

Hardware Implementation:

• implemented in 65 nm CMOS process

Please refer to the following publications for further details:

• [J5] A. Do, S. M. A. Zeinolabedin, and T. Kim, "Energy-Efficient Data-Aware SRAM Design Utilizing Column-based Data Encoding," IEEE Transactions on Circuits and Systems II (TCAS-II), 2020. (link)

• [C9] A. T. Do, S. M. A. Zeinolabedin and T. Kim, "A 0.3 pW/Access 8T Data-Aware SRAM Utilizing Column-based Data Encoding for Ultra-Low Power Applications," IEEE Asian Solid State Circuits Conference (ASSCC), Nov. 2016.(link)