pinout fun
THIS PAGE is a bit like a blog... 'cause, frankly, this relatively simple concept turned into such a huge friggin' ordeal that I can't just let it slide with just a simple diagram. If you really can't even take a moment to acknowledge how danged difficult it was for a friggin' engineer with twenty years' experience in electronics to get this information, (and please consider sending me a donation!), then skip to the bottom of the page for the be-all-end-all completely-functioning pinout diagram (should be there in the next couple days, if not already).
BEWARE: VARIOUS "OFFICIAL" PINOUT SOURCES ACTUALLY SHOW GND Where there's VCC, and vice-versa.
This official SGI 1600SW documentation lists the alleged pinout (quoted below)... http://techpubs.sgi.com/library/tpl/cgi-bin/getdoc.cgi/hdwr/bks/SGI_EndUser/books/O2_FP_Adpt_IG/sgi_html/ch03.html
NOTE THIS PINOUT *DIFFERS* from the official OpenLDI pinout.
FURTHER: This pinout *differs* from the pinout on the PCI card I used, which I determined by following traces.
Here's a pinout from pinouts.ru: http://pinouts.ru/Video/sgi_ldi_pinout.shtml
pinouts.ru has a couple others under different names.
(TODO: Verify all these pinouts with the one I'm actually using... and get rid of the bad ones.)
This table is a *direct copy/paste* from the SGI link above, and MAY NOT BE RIGHT:
These are my notes: From Various Pinouts available online (all of which differ), from trying to read the EDID to following traces on the PCI card which the display worked with, to following traces in the display itself...
Note that some alleged pinouts actually claim VCC where others claim GND, and more!
PINOUT PONDERINGS:
I'm trying to piece-together my notes on the pinout. Several pages of hand-drawn pinouts, and each and every one of them has strike-throughs and notes about "this is wrong!" etc.
I think, as I recall, the pinout at pinouts.ru was ultimately correct, with the minor change that "link 1" and "link 2" are swapped. I NEED TO VERIFY THIS (and the only way to do-so, since my notes are so illegible after all the mark-ups, and there ultimately being at least *two different* pinouts at pinouts.ru, is to trace the pins on my functional-device... I'm using that device to use my computer, so It will be a bit...
UNTIL THEN, here's my logic, as I'm remembering it from these notes:
One thing I remember being especially confusing was "link 1/2" aka "even/odd".
In a dual-channel LVDS setup, what happens is two horizontally-adjacent pixels are sent simultaneously, one on each channel. BESIDES THE ORDER of the pixels, THIS IS IMPORTANT because *one* channel carries the Sync bits, and the other does not.
For the very-first pixel-clock in a row, you'll have the first and second pixels drawn. Now, are these pixels "1" and "2" or pixels "0" and "1"? This is like Big-endian vs Little-endian... there's no single "right" way to do it, and there is no de-facto standard. So, then, the "even" channel could correspond to the left-most pixel in the pair (if they decided to go with 0 being the first pixel), or it could be the right-most pixel in the pair (if they decided to start with pixel 1).
Then, to make things even *more* confusing, there's nothing preventing: e.g. that your GPU might output the first pixel (pixel 0) on its so-called "even" channel, and your display might expect its first pixel to correspond to its "odd" channel (because they started with pixel 1). THEN TO MAKE IT EVEN MORE CONFUSING: Different products *from the same manufacturer* and even *in the same device-series* may use different naming conventions and you may have to piece together lacking-information from different devices' datasheets. AND EVEN MORE CONFUSING THAN THAT: I've seen some data-sheets that flat-out got it wrong. They refer to the left-most pixel as pixel 0, then go-on to call that channel "odd".
Now, onto the pinout at pinouts.ru (of which, actually, there are several... TODO: I need to make sure I reference the right one, here... Or better-yet just draw my own dang pinout and render all these references unnecessary). As I recall, the pinout, there, refers to "link 1" and "link 2", which one would assume to mean that "link 1" corresponds to the *first*/leftmost pixel, and that "link 2" corresponds to the *second*/rightmost pixel (in the pair). In which case, "link 1" should carry the sync-bits.
IN FACT: as I recall, I initially wired it up based on this (totally reasonable?) assumption and got *nada* on the display. There were so many variables as this was my first-attempt at sending it a signal, I assumed it was something else for quite some time and finally in a fit of exhaustion decided to see what would happen if I swapped the channels. Everything was soldered-up, so I ended-up just swapping "Link1" signal 3 with "Link2" signal 3 (signal 3 contains the sync bits)... and low-and-behold, there was video. (I ended-up developing with it connected this way for some time... basically the red and green data was swapped between alternating columns, quite fun). SO, "Link 1" on that pinout actually corresponds to the rightmost pixel in the pair, and "Link 2" corresponds to the leftmost, AND contains the SYNC bits. THIS doesn't match *any* method, it's like saying that the Most-Significant-Bit is bit0 with an on-value of 1 (and the LSB has an on-value of 128?!). This memory seems to be verified in my notes, wherein I actually traced the pins back to the transmitter chips on my video-card, then dug up the pin numbers of the inputs which correspond to the sync-bits, which were grounded on "link 1."
Another memory I'm beginning to recall (from my, at this point, *frantic* notes): The SGI display does *not* use the openLDI pinout. They in fact are different connectors altogether, despite both being miniature versions of centronics-connectors and both being 36 pins. And, again, the pin-mapping is not the same.
FURTHER-STILL: There's Yet Another document, as I recall, FROM SGI, regarding the pinout on the "O2" (Onyx?) graphic-card... and this doesn't match *either*. (Something about the EDID?). I'm going cross-eyed again.
OK, so the various differences found: Some pinouts show tied-low/high on the EDID bus, some actually show VCC where GND is located, some pinouts confuse Link1 vs Link2 vs Odd vs Even (Importantly: SYNC)...
---
OK I've finally dug out the circuit, which, again, is in use *at this moment* to drive the display I'm typing on... Traced it with a multimeter, compared the results to my notes, recompiled my notes and compiled this:
FEMALE, AT GRAPHICS CARD
_______________________________________________________
\ 18 1 /
\ _____________________________________ /
\ | - - - - - - - - - - - - - - - - - - | /
\ | - - - - - - - - - - - - - - - - - - | /
\ ÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻÂŻ /
\ 36 19 /
\_________________________________________/
Channels:
BEWARE: The terms "Odd" and "Even" are *not* reliable standards.
It depends on the designer (and documenter!) of the particular
LVDS transmitter/receiver chip, GPU, PCI-card, LCD, etc.
Do they refer to the first pixel as pixel "0" or pixel "1"?
Then the terms "Odd" and "Even" may be swapped.
The important part is that generally the channel containing the
first pixel is the *only* channel that ALSO contains SYNC bits.
IN THIS PINOUT:
"Odd"
Left-most (first) pixel
CONTAINS SYNC bits
(pinouts.ru refers to this, quite confusingly, as "Link2")
(TI/NS: DS90C387 refers to Odd0-3, as used here, as A0-3)
"Even"
Right-most (second) pixel
DOES NOT contain SYNC bits
(pinouts.ru refers to this, quite confusingly, as "Link1")
(TI/NS: DS90C387 refers to Even0-3, as used here, as A4-7)
1 Odd0-
2 Odd0+
3 Odd1-
4 Odd1+
5 Odd2-
6 Odd2+
7 (N/C)
8 (N/C)
9 GND
10 GND
11 (N/C)
12 (N/C)
13 Even0-
14 Even0+
15 Even1-
16 Even1+
17 Even2-
18 Even2+
19 Odd3-
20 Odd3+
21 OddC-
22 OddC+
23 (N/C) (EDID-SCL*)
24 (N/C) (EDID-VCC*)
25 (N/C) (EDID-SDA*)
26 GND
27 (N/C)
28 GND
29 (N/C)
30 (N/C)
31 (N/C) (LVDS_En*)
32 GND
33 EvenC-
34 EvenC+
35 Even3-
36 Even3+
*: VCC, SCL, SDA, and LVDS_En are unconnected in my circuit, and the following
pinouts haven't been electrically-verified for quite some time.
My old notes state that I read the EDID using the following pinout:
(This pinout was from pinouts.ru, and verified by trace-following on the
PCI card I used to use to drive this display. EXCEPT that pin 24 VCC
is N/C on the PCI card, and the card doesn't seem to send VCC to the display.)
23 SCL
24 VCC (5V)
25 SDA
26 GND
The VGA-converter circuit driving the display (that I'm writing on now)
has the following pinout connecting to the SGI 1600SW
(with a custom EDID going to the computer via VGA):
23 (N/C)
24 (N/C)
25 (N/C)
26 GND
27 (N/C)
28 GND
29-31 (N/C)
The SGI 1600SW documentation (from SGI) claims the following pinout:
(This matches the SGI documentation for the O2 video-card):
SEE NOTE BELOW
23 SCL
24 GND
25 SDA
26-30 VCC
31 LVDS_EN
NOTE:
THIS CONFLICTS with the used/functional-pinout AND SWAPS VCC and GND!
This pinout supplied by SGI was partially-verified as INCORRECT,
based on trace-following on the display's PCBs; pin 24 goes through a
diode before powering the I2C EDID eeprom.
pin 24 >---|>|---> EEPROM-VCC
EEPROM-VCC also appears to be powered internally, so the VCC pins on
the external connector probably needn't be connected at all (which
is corroborated by the PCI card's N/C on these pins)
THERE MAY be some reason for the swapping of VCC/GND, and POSSIBLY the
circuitry inside the SGI 1600SW can handle switching as necessary.
ONE IDEA: Maybe it's related to identifying to the display that it's
connected to an SGI host that can support the color-lock system(?)
REGARDLESS: I was NOT able to read EDID info with the SGI pinout.
LVDS_EN:
Can be ignored in most cases.
This is an output from the monitor to the video-card.
In my PCI card, it's connected as such:
3.3V
^
|
/
\ 4.7k
/
|
LVDS_EN (from display) >---+----|>o-----> LVDS-Transmitter /Power-Down
INTERNALLY: The signal-cable breaks-out into two single-row connectors:
"At the PCB inside the SGI 1600SW":
1 25
_______________________________________________________
|_ . . . . . . . . . . . . . . . . . . . . . . . . . _|
|___________________________________________________|
NOTE: I'm not certain my numbers, here, correspond to the numbers of the
pins... In other words, the order may be reversed
("1" here may actually be 25 on the connector)
Also, is this the male connector at the PCB, or the female
connector that connects at the PCB?
This is compiled from old notes
1 E3+
2 E3-
3 EC+
4 EC-
5 E2+
6 E2-
7 E1+
8 E1-
9 E0+
10 E0-
11 O3+
12 O3-
13 OC+
14 OC-
15 O2+
16 O2-
17 O1+
18 O1-
19 O0+
20 O0-
21 GND
22 GND
23 (N/C)
24 (N/C)
25 (N/C)
10 1
_______________________
| |
| | | | | | | | | | | |
|_______________________|
(See note above!)
External Pin#
1 SDA (25)
2 GND (26)
3 SCL (23)
4 VCC (24)
5 LVDS_EN (31)
6 GND (32)
7 (N/C) (7)
8 (N/C) (8)
9 (N/C) (11)
10 (N/C) (12)
I want to take a moment to thank my new friend for his generous donation which helped motivate my finally compiling this information and making it available to the public. However, if I was paid hourly, even at minimum wage, for merely the *compilation* of this information (forget the actual deriving of it), I'd've needed to request an amount that would make this entire endeavor impossible.
I don't do this stuff for money; if I did this site wouldn't exist. But I would be *really* appreciative, if you find it useful, to please consider, *please* consider sending me some cash, even the random $5 would be highly appreciated (especially just after the middle of the month!) Times are tough.