THEORY 

A synchronous down counter is a type of counter in which all flip-flops are triggered together by the same clock, but the logic is designed so that the count sequence moves in the reverse direction. On every clock pulse, the counter decrements its value instead of incrementing it. Since all stages change simultaneously, the counter avoids ripple delays and produces accurate, high-speed down-counting. The next state of each flip-flop is generated by combinational logic based on the present state, ensuring smooth and predictable downward counting for applications such as timers, event control, and frequency division 

BLOCK DIAGRAM WAVEFORM

VERILOG CODE 

module syn_down_cnt(q,clk,reset);

output reg [3:0] q;

input clk,reset;

// clock divider (same as required)

reg [27:0] clk_div = 0;

wire clk1;

always @(posedge clk)

clk_div = clk_div + 1;

assign clk1 = clk_div[24];

// down counter using divided clock

always @(posedge clk1)

begin

    if(reset)

        q <= 4'd15;   // start from 15

    else

        q <= q - 1;

end

endmodule

TEST BENCH 

module tb_syn_down_cnt();

wire [3:0]q;

reg clk,reset;

syn_down_cnt dux(q,clk,reset);

initial begin

clk=0;

repeat(20)

#5 clk=~clk;

end

initial begin 

reset=1;

#20 reset =0;

#500 reset=1;

end 

endmodule

OUTPUT 

RTL SCHEMATIC POWER 

TIME UTILIZATION REPORT