Theory

Conversion rule (Gray → Binary)

Rule for the most significant bit:

The most significant bit of Binary will be the same as the MSB of Gray.

B_n = G_n

Rule for other Bits:

Each other Binary bit is the XOR of the previous Binary bit and the Gray bit.

B_i = B_(i+1) ⊕ G_i

Truth Table:                         Boolean expression:

Logic diagram:

DATA FLOW DESCRIPTION

Verilog Code :

module Bin_G(G,B);

input [3:0] B;

output [3:0] G;

assign G[0] = B[0]^B[1] ;

assign G[1] = B[1]^B[2] ;

assign G[2] = B[2]^B[3];

assign G[3] = B[3];

endmodule

Test bench :

module TB_Bin_G();

reg [3:0] B;

wire [3:0] G;

Bin_G dux(G,B);

initial 

begin

      B=4'd0;

     #10 B=4'd1;

     #10 B=4'd2;

     #10 B=4'd3;

     #10 B=4'd4;

     #10 B=4'd5;

     #10 B=4'd6;

     #10 B=4'd7;

     #10 B=4'd8;

     #10 B=4'd9;

     #10 B=4'd10;

     #10 B=4'd11;

     #10 B=4'd12;

     #10 B=4'd13;

     #10 B=4'd14;

     #10 B=4'd15;

     #20 $finish();

     end

endmodule

BEHAVIOURAL DESCRIPTION:

verilog code:

module gray_binary (

    input  [3:0] gray,

    output reg [3:0] binary

);

always @(*) begin

    case (gray)

        4'b0000: binary = 4'b0000;

        4'b0001: binary = 4'b0001;

        4'b0010: binary = 4'b0011;

        4'b0011: binary = 4'b0010;

        4'b0100: binary = 4'b0110;

        4'b0101: binary = 4'b0111;

        4'b0110: binary = 4'b0101;

        4'b0111: binary = 4'b0100;

        4'b1000: binary = 4'b1100;

        4'b1001: binary = 4'b1101;

        4'b1010: binary = 4'b1111;

        4'b1011: binary = 4'b1110;

        4'b1100: binary = 4'b1010;

        4'b1101: binary = 4'b1011;

        4'b1110: binary = 4'b1001;

        4'b1111: binary = 4'b1000;

        default: binary = 4'b0000;

    endcase

end

endmodule

testbench:

module tb_gray_binary;

reg  [3:0] gray;

wire [3:0] binary;

gray_binary dut (

    .gray(gray),

    .binary(binary)

);

integer i;

initial begin

    for (i = 0; i < 16; i = i + 1) begin

        gray = i[3:0];

        #1;

    end

    $finish;

end

endmodule

O/P obtained:

Pin Assignment

 i\p:- J15,L16,M13,R15 o\p:- H17,K15,J13,,N14  

RTL SCHEMATIC POWER 

TIME UTILIZATION REPORT