Theory :

• A combinational circuit that selects one of 16 input lines (D0–D15) and routes it to a single output (Y) based on 4 select lines (S3, S2, S1, S0). Inputs: 16 data inputs, 4 select inputs

• Output: 1 output line

• Selection Logic: The binary value of the select lines determines which input is passed to the output.

truth table :                                        boolean expression :

Block diagram :

DATA FLOW DESCRIPTION

verilog code 

module mux16to1 (

    input wire d0, d1, d2, d3, d4, d5, d6, d7,

    input wire d8, d9, d10, d11, d12, d13, d14, d15,  // 16 data inputs

    input wire s0, s1, s2, s3,                        // 4 select lines

    output wire y                                     // Output

);

assign y = (~s3 & ~s2 & ~s1 & ~s0 & d0)  |

           (~s3 & ~s2 & ~s1 &  s0 & d1)  |

           (~s3 & ~s2 &  s1 & ~s0 & d2)  |

           (~s3 & ~s2 &  s1 &  s0 & d3)  |

           (~s3 &  s2 & ~s1 & ~s0 & d4)  |

           (~s3 &  s2 & ~s1 &  s0 & d5)  |

           (~s3 &  s2 &  s1 & ~s0 & d6)  |

           (~s3 &  s2 &  s1 &  s0 & d7)  |

           ( s3 & ~s2 & ~s1 & ~s0 & d8)  |

           ( s3 & ~s2 & ~s1 &  s0 & d9)  |

           ( s3 & ~s2 &  s1 & ~s0 & d10) |

           ( s3 & ~s2 &  s1 &  s0 & d11) |

           ( s3 &  s2 & ~s1 & ~s0 & d12) |

           ( s3 &  s2 & ~s1 &  s0 & d13) |

           ( s3 &  s2 &  s1 & ~s0 & d14) |

           ( s3 &  s2 &  s1 &  s0 & d15);

endmodule

testbench 

module tb_mux16to1;

reg d0, d1, d2, d3, d4, d5, d6, d7;

reg d8, d9, d10, d11, d12, d13, d14, d15;

reg s0, s1, s2, s3;

wire y;

// Instantiate the MUX

mux16to1 DUT (

    .d0(d0), .d1(d1), .d2(d2), .d3(d3),

    .d4(d4), .d5(d5), .d6(d6), .d7(d7),

    .d8(d8), .d9(d9), .d10(d10), .d11(d11),

    .d12(d12), .d13(d13), .d14(d14), .d15(d15),

    .s0(s0), .s1(s1), .s2(s2), .s3(s3),

    .y(y)

);

initial begin

    // Initialize data inputs

    {d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15} = 16'b0101010101010101;

    // Test all select lines

    s3 = 0; s2 = 0; s1 = 0; s0 = 0; #10;

    s3 = 0; s2 = 0; s1 = 0; s0 = 1; #10;

    s3 = 0; s2 = 0; s1 = 1; s0 = 0; #10;

    s3 = 0; s2 = 0; s1 = 1; s0 = 1; #10;

    s3 = 0; s2 = 1; s1 = 0; s0 = 0; #10;

    s3 = 0; s2 = 1; s1 = 0; s0 = 1; #10;

    s3 = 0; s2 = 1; s1 = 1; s0 = 0; #10;

    s3 = 0; s2 = 1; s1 = 1; s0 = 1; #10;

    s3 = 1; s2 = 0; s1 = 0; s0 = 0; #10;

    s3 = 1; s2 = 0; s1 = 0; s0 = 1; #10;

    s3 = 1; s2 = 0; s1 = 1; s0 = 0; #10;

    s3 = 1; s2 = 0; s1 = 1; s0 = 1; #10;

    s3 = 1; s2 = 1; s1 = 0; s0 = 0; #10;

    s3 = 1; s2 = 1; s1 = 0; s0 = 1; #10;

    s3 = 1; s2 = 1; s1 = 1; s0 = 0; #10;

    s3 = 1; s2 = 1; s1 = 1; s0 = 1; #10;

    $finish;

end

endmodule

BEHAVIORAL DESCRIPTION:

verilog code:

module mux16_1(

    output reg y,

    input [3:0] s,

    input [15:0] i

);

always @(*) begin

    case(s)

        4'b0000: y = i[0];

        4'b0001: y = i[1];

        4'b0010: y = i[2];

        4'b0011: y = i[3];

        4'b0100: y = i[4];

        4'b0101: y = i[5];

        4'b0110: y = i[6];

        4'b0111: y = i[7];

        4'b1000: y = i[8];

        4'b1001: y = i[9];

        4'b1010: y = i[10];

        4'b1011: y = i[11];

        4'b1100: y = i[12];

        4'b1101: y = i[13];

        4'b1110: y = i[14];

        4'b1111: y = i[15];

    endcase

end

endmodule

testbench:

`timescale 1ns/1ps

module tb_mux16_1;

  reg [3:0] s;

  reg [15:0] i;

  wire y;

  mux16_1 DUT(y, s, i);

  initial begin

    i = 16'b1010_1100_1111_0001;  // Test inputs

    s = 4'b0000; #10;

    s = 4'b0001; #10;

    s = 4'b0010; #10;

    s = 4'b0011; #10;

    s = 4'b0100; #10;

    s = 4'b0101; #10;

    s = 4'b0110; #10;

    s = 4'b0111; #10;

    s = 4'b1000; #10;

    s = 4'b1001; #10;

    s = 4'b1010; #10;

    s = 4'b1011; #10;

    s = 4'b1100; #10;

    s = 4'b1101; #10;

    s = 4'b1110; #10;

    s = 4'b1111; #10;

    $finish;

  end

endmodule

output obtained :

Pin Assignment

RTL SCHEMATIC POWER 

TIME UTILIZATION REPORT