Theory

An 8:3 encoder is a combinational logic circuit that converts 8 input lines into a 3-bit binary code. Here's a concise overview:

• Inputs: 8 lines (D0 to D7), each representing a unique signal.

• Outputs: 3 bits (Y2, Y1, Y0) that encode the position of the active input.

• Function: It outputs the binary representation of the highest-priority active input.

Truth table                  bollean expression 

logic diagram

DATA FLOW DESCRIPTION

verilog code 

module encoder8to3 (

    input  wire [7:0] d,  // 8 inputs d0..d7

    output wire [2:0] y   // 3-bit output

);

    assign y[2] = d[4] | d[5] | d[6] | d[7];

    assign y[1] = d[2] | d[3] | d[6] | d[7];

    assign y[0] = d[1] | d[3] | d[5] | d[7];

endmodule

testbench 

module tb_encoder8to3;

reg [7:0] d;

wire [2:0] y;

encoder8to3 uut (d,y);

initial begin

     d = 8’d01; #10; // d0

     d = 8’d3; #10; // d1

     d = 8’d7; #10; // d2

     d = 8’d15; #10; // d3

     d = 8’d31; #10; // d4

     d = 8’d63; #10; // d5

     d = 8’d127; #10; // d6

     d = 8’d255; #10; // d7

     $finish;

end

endmodule

BEHAVIORAL DESCRIPTION:

verilog code:

module enc8_3(y, i);

    output reg [2:0] y;   

    input [7:0] i;        

    always @(i)

     begin

        y = 3'b000;       

        casex (i)         

            8'b0000_0001: y = 3'b000;

            8'b0000_001x: y = 3'b001;  

            8'b0000_01xx: y = 3'b010;  

            8'b0000_1xxx: y = 3'b011; 

            8'b0001_xxxx: y = 3'b100;  

            8'b001x_xxxx: y = 3'b101;  

            8'b01xx_xxxx: y = 3'b110;  

            8'b1xxx_xxxx: y = 3'b111;  

            default: y = 3'b000;

        endcase

    end

endmodule

testbench:

module tb_enc8_3;

  reg [7:0] i;       

  wire [2:0] y;     

  enc8_3 DUT(y, i);

  initial begin

    i = 8'b0000_0001; #10;

    i = 8'b0000_0010; #10;

    i = 8'b0000_0100; #10;

    i = 8'b0000_1000; #10;

    i = 8'b0001_0000; #10;

    i = 8'b0010_0000; #10;

    i = 8'b0100_0000; #10;

    i = 8'b1000_0000; #10;

    $finish;

  end

endmodule

output obtained :