A D flip-flop (Data or Delay flip-flop) is a clocked memory device that captures the value of the input (D) at a specific clock edge and holds it until the next clock event.
Inputs:
D (Data): The value to be stored
CLK (Clock): Controls when the data is sampled
Outputs:
Q: Stored output
Q̅: Complement of Q
module dff(q,qb,d,clk);
input d,clk;
output q,qb;
reg q=0;
reg qb=1;
always @(posedge clk)
begin
q = d;
qb <= ~q;
end
endmodule
module tb_dff();
wire q,qb;
reg d,clk;
dff dux(q,qb,d,clk);
initial
begin
clk = 0;
repeat(10)
begin
#5 clk =~clk;
end
end
initial
begin
d = 0;
#10 d = 1;
#10 d = 0;
#10 d = 1;
#20 $finish;
end
endmodule