Theory 

Gray code (sometimes referred to as reflected binary code) is a binary numeral system in which two successive values differ in only one bit.

Gray code helps to minimize potential errors in digital systems, for example in mechanical encoders and error correction

Conversion Rule (Binary → Gray)

MSB Rule:  The most significant bit (MSB) of the Gray code is the same as the MSB of the binary number.

Gn=Bn

where Bn= MSB of Binary, Gn​ = MSB of Gray

Other Digits Rule: Each next Gray code digit will be the XOR of the current binary digit with the previous binary digit.

Gi​=Bi+1​⊕Bi​

Truth Table:                    Boolean expression:

Logic diagram:

DATA FLOW DESCRIPTION 

Verilog Code :

module Bin_G(G,B);

input [3:0] B;

output [3:0] G;

assign G[0] = B[0]^B[1] ;

assign G[1] = B[1]^B[2] ;

assign G[2] = B[2]^B[3];

assign G[3] = B[3];

endmodule

Test bench :

module TB_Bin_G();

reg [3:0] B;

wire [3:0] G;

Bin_G dux(G,B);

initial 

begin

      B=4'd0;

     #10 B=4'd1;

     #10 B=4'd2;

     #10 B=4'd3;

     #10 B=4'd4;

     #10 B=4'd5;

     #10 B=4'd6;

     #10 B=4'd7;

     #10 B=4'd8;

     #10 B=4'd9;

     #10 B=4'd10;

     #10 B=4'd11;

     #10 B=4'd12;

     #10 B=4'd13;

     #10 B=4'd14;

     #10 B=4'd15;

     #20 $finish();

     end

endmodule

BEHAVIOURAL DESCRIPTION:

verilog code :

module binary_gray (

    input  [3:0] binary,

    output reg [3:0] gray

);

always @(*) begin

    case (binary)

        4'b0000: gray = 4'b0000;

        4'b0001: gray = 4'b0001;

        4'b0010: gray = 4'b0011;

        4'b0011: gray = 4'b0010;

        4'b0100: gray = 4'b0110;

        4'b0101: gray = 4'b0111;

        4'b0110: gray = 4'b0101;

        4'b0111: gray = 4'b0100;

        4'b1000: gray = 4'b1100;

        4'b1001: gray = 4'b1101;

        4'b1010: gray = 4'b1111;

        4'b1011: gray = 4'b1110;

        4'b1100: gray = 4'b1010;

        4'b1101: gray = 4'b1011;

        4'b1110: gray = 4'b1001;

        4'b1111: gray = 4'b1000;

        default: gray = 4'b0000;

    endcase

end

endmodule 

test bench:

module tb_binary_gray;

reg  [3:0] binary;

wire [3:0] gray;

binary_gray dut (

    .binary(binary),

    .gray(gray)

);

integer i;

initial begin

    for (i = 0; i < 16; i = i + 1) begin

        binary = i[3:0];

        #1;

    end

    $finish;

end

endmodule 

O/P obtained:

Pin Assignment

 i\p:- J15,L16,M13,R15 o\p:- H17,K15,J13,,N14