Theory 

A 4-bit Ripple Carry Adder (RCA) adds two 4-bit binary numbers using four connected full adders. Each adder passes its carry to the next, causing a ripple effect. It outputs a 4-bit sum and a final carry-out. Simple but slower due to carry propagation.

Boolean expression :

sum0 = a0 ^ b0 ^ cin

c1   = (a0 & b0) | (b0 & cin) | (a0 & cin)

sum1 = a1 ^ b1 ^ c1

c2   = (a1 & b1) | (b1 & c1) | (a1 & c1)

sum2 = a2 ^ b2 ^ c2

c3   = (a2 & b2) | (b2 & c2) | (a2 & c2)

sum3 = a3 ^ b3 ^ c3

cout = (a3 & b3) | (b3 & c3) | (a3 & c3)

logic diagram :

DATA FLOW DESCRIPTION

verilog code:

module rca4_df (

    input  wire [3:0] a, b,   // 4-bit operands

    input  wire cin,       // carry-in

    output wire [3:0] sum, // 4-bit sum

    output wire cout       // carry-out

    );

    // Internal carry wires

    wire c1, c2, c3;

    // Bit 0

    assign sum[0] = a[0] ^ b[0] ^ cin;

    assign c1 = (a[0] & b[0]) | (b[0] & cin) | (a[0] & cin);

// Bit 1

    assign sum[1] = a[1] ^ b[1] ^ c1;

    assign c2 = (a[1] & b[1]) | (b[1] & c1) | (a[1] & c1);

    // Bit 2

    assign sum[2] = a[2] ^ b[2] ^ c2;

    assign c3 = (a[2] & b[2]) | (b[2] & c2) | (a[2] & c2);

    // Bit 3

    assign sum[3] = a[3] ^ b[3] ^ c3;

    assign cout = (a[3] & b[3]) | (b[3] & c3) | (a[3] & c3);

endmodule

test bench 

module tb_rca4_df;

    reg [3:0] a, b;

    reg cin;

    wire [3:0] sum;

    wire cout;

        rca4_df uut (a,b,cin,sum,cout);

    initial begin

// Test cases

        a=4'b0000; b=4'b0000; cin=0; #10;

        a=4'b0001; b=4'b0010; cin=0; #10;

        a=4'b0101; b=4'b0011; cin=0; #10;

        a=4'b1111; b=4'b0001; cin=0; #10;

        a=4'b1010; b=4'b0101; cin=1; #10;

        $finish;

    end

endmodule

BEHAVIORAL DESCRIPTION:

verilog code:

module n4_bcd (

    input  [3:0] A,

    input  [3:0] B,

    input        Cin,

    output reg [3:0] Sum,

    output reg       Cout

);

always @(*) begin

    {Cout, Sum} = A + B + Cin;

end

endmodule

testbench:

module tb_n4_bcd;

reg  [3:0] A, B;

reg        Cin;

wire [3:0] Sum;

wire       Cout;

n4_bcd dut (

    .A(A),

    .B(B),

    .Cin(Cin),

    .Sum(Sum),

    .Cout(Cout)

);

initial begin

    A = 4'b1010; B = 4'b0101; Cin = 1'b0;

    #10;

    A = 4'b1111; B = 4'b0001; Cin = 1'b0;

    #10;

    A = 4'b0001; B = 4'b0011; Cin = 1'b1;

    #10;

    $stop;

end

endmodule

output obtained 

Pin Assignment

 i\p:- J15,L16,M13 o\p:-H17,K15