A 4:1 Multiplexer (MUX) selects one of four input signals and forwards it to a single output line based on two select lines.
Inputs: D0, D1, D2, D3
Select lines: S1, S0
Output: Y
truth table : boolean expression:
module mux4to1 (
input wire d0, d1, d2, d3, // inputs
input wire s0, s1, // select lines
output wire y // output
);
assign y = (~s1 & ~s0 & d0) |
(~s1 & s0 & d1) |
( s1 & ~s0 & d2) |
( s1 & s0 & d3);
endmodule
module tb_mux4to1;
reg d0, d1, d2, d3;
reg s0, s1;
wire y;
mux4to1 uut (do,d1,d2,d3,s0,s1,y);
initial begin
d0=0; d1=1; d2=0; d3=1;
{s1,s0}=2'b00; #10;
{s1,s0}=2'b01; #10;
{s1,s0}=2'b10; #10;
{s1,s0}=2'b11; #10;
// Test case 2
d0=1; d1=0; d2=1; d3=0;
{s1,s0}=2'b00; #10;
{s1,s0}=2'b01; #10;
{s1,s0}=2'b10; #10;
{s1,s0}=2'b11; #10;
$finish;
end
endmodule
module mux4_1(
output reg y,
input [1:0] s,
input [3:0] i
);
always @(*) begin
case(s)
2'b00: y = i[0];
2'b01: y = i[1];
2'b02: y = i[2];
2'b03: y = i[3];
endcase
end
endmodule
module tb_mux4_1;
reg [1:0] s;
reg [3:0] i;
wire y;
mux4_1 DUT(y, s, i);
initial begin
i = 4'b1101; // Inputs
s = 2'b00; #10;
s = 2'b01; #10;
s = 2'b10; #10;
s = 2'b11; #10;
$finish;
end
endmodule
i\p:- J15,L16 o\p:-H17