Theory 

A 4-bit Carry Lookahead Adder (CLA) adds two 4-bit numbers quickly by calculating carry bits in parallel using generate and propagate logic. It’s faster than ripple carry adders because it avoids waiting for carry to ripple through each bit.

Boolean expression :

Pi = Ai ^ Bi    // propagate

Gi = Ai & Bi    // generate

Carry equations:   Ci=Gi-1|(pi-1&Ci-1)

C0 = cin

C1 = G0 | (P0 & C0)

C2 = G1 | (P1 & C1) = G1 | (P1 & G0) | (P1 & P0 & C0)

C3 = G2 | (P2 & C2) = G2 | (P2 & G1) | (P2 & P1 & G0) | (P2 & P1 & P0 & C0)

C4 = G3 | (P3 & C3) = G3 | (P3 & G2) | (P3 & P2 & G1) | (P3 & P2 & P1 & G0) | (P3 & P2 & P1 & P0 & C0)

Sum

Si = Pi ^ Ci

logic diagram 

DATA FLOW DESCRIPTION

verilog code 

module cla4_df (

    input  wire [3:0] a, b,   // 4-bit operands

    input  wire cin,       // carry-in

    output wire [3:0] sum, // 4-bit sum

    output wire cout       // carry-out);

    wire [3:0] p, g;   // propagate and generate

    wire c1, c2, c3;   // internal carries

    // Propagate and generate

    assign p = a ^ b;

    assign g = a & b;

    // Carry logic

    assign c1 = g[0] | (p[0] & cin);

    assign c2 = g[1] | (p[1] & g[0]) | (p[1] & p[0] & cin);

    assign c3 = g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & cin);

    assign cout = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]) | (p[3] & p[2] & p[1] & p[0] & cin);

    // Sum

    assign sum[0] = p[0] ^ cin;

    assign sum[1] = p[1] ^ c1;

    assign sum[2] = p[2] ^ c2;

    assign sum[3] = p[3] ^ c3;

endmodule

 testbench 

module tb_cla4_df;

    reg [3:0] a, b;

    reg cin;

    wire [3:0] sum;

    wire cout;

    // Instantiate CLA

    cla4_df uut (a,b,cin,sum,cout);

    initial begin

        // Test cases

        a = 4'b0000; b = 4'b0000; cin = 0; #10;

        a = 4'b0001; b = 4'b0010; cin = 0; #10;

        a = 4'b0101; b = 4'b0011; cin = 0; #10;

        a = 4'b1111; b = 4'b0001; cin = 0; #10;

        a = 4'b1010; b = 4'b0101; cin = 1; #10;

        a = 4'b1111; b = 4'b1111; cin = 1; #10;

        $finish;

    end

endmodule

BEHAVIORAL DESCRIPTION:

verilog code:

module cla (

    input  [3:0] a,

    input  [3:0] b,

    input        cin,

    output reg [3:0] sum,

    output reg       cout

);

reg [3:0] p,g;

reg c1,c2,c3,c4;

always @(*) begin

    p = a ^ b;

    g = a & b;

    c1 = g[0] | (p[0] & cin);

    c2 = g[1] | (p[1] & g[0]) | (p[1] & p[0] & cin);

    c3 = g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & cin);

    c4 = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1]) |

         (p[3] & p[2] & p[1] & g[0]) |

         (p[3] & p[2] & p[1] & p[0] & cin);

    sum[0] = p[0] ^ cin;

    sum[1] = p[1] ^ c1;

    sum[2] = p[2] ^ c2;

    sum[3] = p[3] ^ c3;

    cout = c4;

end

endmodule

testbench :

module tb_cla;

reg  [3:0] a, b;

reg        cin;

wire [3:0] sum;

wire       cout;

cla DUT (a, b, cin, sum, cout);

initial begin

    a=4'b0000; b=4'b0000; cin=0; #10;

    a=4'b0001; b=4'b0101; cin=0; #10;

    a=4'b1111; b=4'b0001; cin=0; #10;

    a=4'b0001; b=4'b1111; cin=1; #10;

    a=4'b1010; b=4'b0001; cin=0; #10;

    a=4'b1111; b=4'b0101; cin=1; #10;

    a=4'b0111; b=4'b1111; cin=1; #10;

    $finish;

end

endmodule

output obtained:

Pin Assignment

i\p:- J15,L16,M13 o\p:-H17,K15