A combinational circuit that selects one of 8 input lines (D0–D7) and routes it to a single output (Y) based on 3 select lines (S2, S1, S0). Inputs: 8 data inputs, 3 select inputs
Output: 1 output line
Selection Logic: The binary value of the select lines determines which input is passed to the output.
truth table boolean expression:
module mux (
input wire d0, d1, d2, d3, // Data inputs
input wire s0, s1, // Select inputs
output wire y // Output
);
assign y = (~s1 & ~s0 & d0) | // When s1s0 = 00
(~s1 & s0 & d1) | // When s1s0 = 01
( s1 & ~s0 & d2) | // When s1s0 = 10
( s1 & s0 & d3); // When s1s0 = 11
endmodule
module tb_mux;
reg d0, d1, d2, d3;
reg s0, s1;
wire y;
// Instantiate the MUX
mux DUT (
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.s0(s0),
.s1(s1),
.y(y)
);
initial begin
// Test case 1: select d0
d0 = 0; d1 = 1; d2 = 0; d3 = 1;
s1 = 0; s0 = 0;
#10;
// Test case 2: select d1
s1 = 0; s0 = 1;
#10;
// Test case 3: select d2
s1 = 1; s0 = 0;
#10;
// Test case 4: select d3
s1 = 1; s0 = 1;
#10;
end
endmodule
module mux8_1(y,s,i);
output y;
input [2:0]s;
input [7:0]i;
reg y;
always@(s,i)
begin
case(s)
3'b000: y=i[0];
3'b001: y=i[1];
3'b010: y=i[2];
3'b011: y=i[3];
3'b100: y=i[4];
3'b101: y=i[5];
3'b110: y=i[6];
3'b111: y=i[7];
endcase
end
endmodule
module tb_mux8_1;
reg [2:0] s;
reg [7:0] i;
wire y;
mux8_1 DUT(y, s, i);
initial begin
i = 8'b10101010;
s = 3'b000; #10;
s = 3'b001; #10;
s = 3'b010; #10;
s = 3'b011; #10;
s = 3'b100; #10;
s = 3'b101; #10;
s = 3'b110; #10;
s = 3'b111; #10;
$finish;
end
endmodule