Theory 

A 2-to-4 line decoder is a combinational logic circuit that takes 2 input bits and activates one of 4 output lines, based on the binary value of the inputs.

• Inputs: 2 bits → A_1, A_0

• Outputs: 4 lines → Y_0, Y_1, Y_2, Y_3

• Enable: Optional control input to activate the decoder

truth table                                boolean expression:

logic diagram 

DATA FLOW DESCRIPTION

verilog code

module decoder2to4_en_df (

    input  wire a1, a0,  // 2-bit input

    input  wire en,  // enable

    output wire y0, y1, y2, y3 // 4-bit output

);

    assign y0 = en & ~a1 & ~a0;

    assign y1 = en & ~a1 &  a0;

    assign y2 = en &  a1 & ~a0;

    assign y3 = en &  a1 &  a0;

endmodule

test bench

module tb_decoder2to4_en_df;

reg a1, a0, en;

wire y0, y1, y2, y3;

decoder2to4_en_df uut (a1,a0,en,y0,y1,y2,y3);

initial begin

// Test when enable is 0 (all outputs should be 0)

     en = 0; a1=0; a0=0; #10;

     en = 0; a1=0; a0=1; #10;

     en = 0; a1=1; a0=0; #10;

     en = 0; a1=1; a0=1; #10;

     // Test when enable is 1

     en = 1; a1=0; a0=0; #10;

     en = 1; a1=0; a0=1; #10;

     en = 1; a1=1; a0=0; #10;

     en = 1; a1=1; a0=1; #10;

     $finish;

end

endmodule

BEHAVIORAL DESCRIPTION:

verilog code:

module dec2_4(

    output reg [3:0] y,

    input [1:0] a,

    input en

);

always @(*) begin

    if (!en)

        y = 4'b0000;

    else begin

        case (a)

            2'b00: y = 4'b0001;

            2'b01: y = 4'b0010;

            2'b02: y = 4'b0100;

            2'b03: y = 4'b1000;

        endcase

    end

end

endmodule

testbench:

`timescale 1ns/1ps

module tb_dec2_4;

  reg [1:0] a;

  reg en;

  wire [3:0] y;

  dec2_4 DUT(y, a, en);

  initial begin

    en = 1;     // Enable ON

    a = 2'b00; #10;

    a = 2'b01; #10;

    a = 2'b10; #10;

    a = 2'b11; #10;

    // Test with Enable OFF

    en = 0; a = 2'b10; #10;

    $finish;

  end

endmodule

output obtained