Embedded Files
Steps to create a Verilog file
Step 01: Create project link.
Step 02: Enter the project name and the path where you are storing this project on your device.
Step 03: Select RTL project option.
Step 04: On 'add source page' do not make any changes and click next.
Step 05: On 'Constraint' do not make any changes and click on next.
Step 06: Now select the type of board to be used [FPGA board].
Step 07: Now click on design source.
Step 08: Select add create design source.
Step 09: Now enter the file name.
Step 10: Now select 'simulation'.
Step 11: Now select add/create simulation source.
Step 12: Create file.
Step 13: Now write the Verilog code in design source file.
Step 14: Write the Test Bench code for debugging the code (Verilog code) in simulation tab.
Step 15: Now, you can see the graph with inputs and outputs.
GATES
1. AND Gate
Logic Diagram: Truth Table:
Verilog Code:
module and2_1 (Y, A, B);
input A, B;
output Y;
assign Y = A & B;
endmodule
Test Bench
module tb_and2_1();
reg A, B;
wire Y;
and2_1 DUT (Y, A, B);
initial
begin
A = 1'b0; B = 1'b0;
#10 A = 1'b0; B = 1'b1;
#10 A = 1'b1; B = 1'b0;
#10 A = 1'b1; B = 1'b1;
#20 $finish;
end
endmodule
Output:
Pin Assignment:
Input A = J15
Input B = L16
Output Y = H17
2. OR Gate
Logic Diagram: Truth Table:
Verilog Code:
module or2_1 (Y, A, B);
input A, B;
output Y;
assign Y = A | B;
endmodule
Test Bench
module tb_or2_1();
reg A, B;
wire Y;
or2_1 DUT (Y, A, B);
initial
begin
A = 1'b0; B = 1'b0;
#10 A = 1'b0; B = 1'b1;
#10 A = 1'b1; B = 1'b0;
#10 A = 1'b1; B = 1'b1;
#20 $finish;
end
endmodule
Output:
> Pin Assignment:
Input A = J15
Input B = L16
Output Y = H17
3. NAND Gate
> Logic Diagram: >Truth Table:
Verilog Code:
module nand2_1(Y,A,B);
input A,B;
output Y;
assign Y=~(A&B);
endmodule
Test Bench:
module tb_nand2_1();
reg A,B;
wire Y;
nand2_1 DUT(Y,A,B);
initial
begin
A=1'b0; B=1'b0;
#10 A=1'b0; B=1'b1;
#10 A=1'b1; B=1'b0;
#10 A=1'b1; B=1'b1;
#20 $finish();
end
endmodule
Output:
Pin Assignment:
Input A = J15
Input B = L16
Output Y = H17
4. NOR Gate
>Logic Diagram: >Truth Table:
> Verilog Code:
module nor2_1(Y,A,B);
input a,b;
output Y;
assign Y=~(A|B);
endmodule
Test Bench:
module tb_nor2_1();
reg A,B;
wire Y;
nor2_1 DUT(Y,A,B);
initial
begin
A=1'b0; B=1'b0;
#10 A=1'b0; B=1'b1;
#10 A=1'b1; B=1'b0;
#10 A=1'b1; B=1'b1;
#20 $finish();
end
endmodule
Output:
> Pin Assignment:
Input A = J15
Input B = L16
Output Y = H17
5. XOR Gate
> Logic Diagram: >Truth Table:
Verilog Code:
module xor2_1(Y,A,B);
input A,B;
output Y;
assign Y=(A^B);
endmodule
Test Bench:
module tb_xor2_1();
reg A,B;
wire Y;
xor2_1 DUT(Y,A,B);
initial
begin
A=1'b0; B=1'b0;
#10 A=1'b0; B=1'b1;
#10 A=1'b1; B=1'b0;
#10 A=1'b1; B=1'b1;
#20 $finish();
end
endmodule
Output:
Pin Assignment:
Input A = J15
Input B = L16
Output Y = H17
6. XNOR Gate
> Logic Diagram: > Truth Table:
Verilog Code:
module xnor2_1(Y,A,B);
input A,B;
output Y;
assign Y=~(A^B);
endmodule
Test Bench:
module tb_xnor2_1();
reg A,B;
wire Y;
xnor2_1 DUT(Y,A,B);
initial
begin
A=1'b0; B=1'b0;
#10 A=1'b0; B=1'b1;
#10 A=1'b1; B=1'b0;
#10 A=1'b1; B=1'b1;
#20 $finish();
end
endmodule
Output:
Pin Assignment:
Input A = J15
Input B = L16
Output Y = H17
7. NOT Gate
>Logic Diagram: > Truth Table:
Verilog Code:
module not1_1(Y,A);
input A;
output Y;
assign Y= ~A;
endmodule
Test Bench:
module tb_not1_1();
reg A;
wire Y;
not1_1 DUT(Y,A);
initial
begin
A=1'b0;
#10 A=1'b1;
#20 $finish();
end
endmodule
Output:
Pin Assignment:
Input A = J15
Output Y = H17
HALF ADDER
> Block Diagram: > Truth Table:
Verilog Code:
module half_adder(s,c,a,b);
input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule
Test Bench:
module tb_half_adder();
reg a,b;
wire s,c;
half_adder DUT(s,c,a,b);
initial
begin
a=1'b0; b=1'b0;
#10 a=1'b0; b=1'b1;
#10 a=1'b1; b=1'b0;
#10 a=1'b1; b=1'b1;
#20 $finish();
end
endmodule
Output:
Pin Assignment:
Input a = J15
Input b = L16
Output s = H17
Output c = K15
FULL ADDER
> Block Diagram: > Truth Table:
Verilog Code:
module full_adder(s,cin,a,b,c);
input a,b,c;
output s,cin;
assign s= a^b^c;
assign cin=(a&b)|(b&c)|(a&c);
endmodule
Test Bench:
module tb_full_adder();
reg a,b,c;
wire s,cin;
full_adder DUT(s,cin,a,b,c);
initial
begin
a=1'b0; b=1'b0; c=1'b0;
#10 a=1'b0; b=1'b0; c=1'b1;
#10 a=1'b0; b=1'b1; c=1'b0;
#10 a=1'b0; b=1'b1; c=1'b1;
#10 a=1'b1; b=1'b0; c=1'b0;
#10 a=1'b1; b=1'b0; c=1'b1;
#10 a=1'b1; b=1'b1; c=1'b0;
#10 a=1'b1; b=1'b1; c=1'b1;
#20 $finish;
end
endmodule
Output:
> Pin Assignment:
Input a = J15
Input b = L16
Input c = M13
Output s = H17
Output cin = K15
HALF SUBTRACRTOR
>Block Diagram: > Truth Table:
Verilog Code:
module half_subtractor(diff,bo, a, b);
input a, b;
output diff,bo;
assign diff = a ^ b;
assign bo = (~a) & (b);
endmodule
Test Bench:
module tb_half_subtractor();
reg a,b;
wire diff,bo;
half_subtractor DUT(diff,bo, a, b);
initial
begin
a=1'b0; b=1'b0;
#10 a=1'b0; b=1'b1;
#10 a=1'b1; b=1'b0;
#10 a=1'b1; b=1'b1;
#20 $finish();
end
endmodule
Output:
Pin Assignment:
Input a = J15
Input b = L16
Output s = H17
Output c = K15
FULL SUBTRACTOR
> Block Diagram: > Truth Table:
Verilog Code:
module full_sub(diff, bo, a, b, c);
input a, b, c;
output diff, bo;
assign diff = a ^ b ^ c;
assign bo = (~a & b) | (~a & c) | (b & c);
endmodule
Test Bench:
module tb_full_sub();
reg a, b, c;
wire diff, bo;
full_sub DUT(diff, bo, a, b, c);
initial
begin
a=1'b0; b=1'b0; c=1'b0;
#10 a=1'b0; b=1'b0; c=1'b1;
#10 a=1'b0; b=1'b1; c=1'b0;
#10 a=1'b0; b=1'b1; c=1'b1;
#10 a=1'b1; b=1'b0; c=1'b0;
#10 a=1'b1; b=1'b0; c=1'b1;
#10 a=1'b1; b=1'b1; c=1'b0;
#10 a=1'b1; b=1'b1; c=1'b1;
#20 $finish();
end
endmodule
Output:
Pin Assignment:
Input a = J15
Input b = L16
Input c = M13
Output diff = H17
Output bo = K15
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