Nick's Blog: Research at Rutgers WINLAB

UPDATED!

(keeping background though)

Some Background:

I'm Nick Cooper, rising senior(finally)

I got into a summer Internship offered at Rutgers University at the research center WINLAB:

http://www.winlab.rutgers.edu/

http://summer.winlab.rutgers.edu/

WINLAB is a network/general software development center in New Brunswick. One of the major aspects/features of this center is the 20x20 grid of server nodes used for networking/sdr/radio stuff. That's 400 programmable nodes on the ceiling. (There are pictures on the websites)

There are many projects going on at the internship including, VR, MF, security (mobile/pc), and many others.

The project I am working on is a subdivision of the larger SDR project. For those who don't know, SDR stands for Software Defined Radio which implements traditionally hardware only radio functionality (ASIC stuff) onto general purpose CPUs/FPGAs using software. At this internship there are 3 main groups doing SDR stuff. Spectrum Sensing(mine), location(indoor), and LTE-unlicensed. There are two subdivisions of the spectrum sensing group (each with 2 people), FPGA/VHDL and CPU. I am doing work with the vhdl subgroup. VHDL stands for (Very High Speed Integrate Circuit Hardware Description Language) and FPGA stands for (Field Programmable Gate Array).

http://www.xilinx.com/products/silicon-devices/fpga.html link to a major FPGA manufacturing site.

FPGAs are kinda like SUPER arduinos--basically you write code in either VHDL(what I'm using) Verilog or System Verilog and then implement the design at the gate level onto a customizable chip(small scale cpu) with x ammount of LUTs, FFs, RAM etc...depending on which FPGA you have

No More Background because its boring

(previous post)

I have been at WINLAB for about 2 weeks now, I started the 29 of June.

So far, I have learned how to write basic VHDL code and implement it onto the FPGA we were supplied with (Xilinx ZedBoard). So far I have made a few simple programs both combinatoric and sequential logic. D*** more explaining... Combinatoric logic is basic gate level logic circuits (series of AND/OR/XNOR gates and stuff) while sequential logic requires the use of a clock signal and usually D FFs (flip flops). The types of programs I have made are: simple combinatoric stuff (and gates etc), more advanced sequential binary counters and low level multiplexers. Attached are some pics of both code and simulation waveforms.

(first update)

This is now the start of my 3rd full week at WINLAB(Monday)

Some fun stuff happened last week involving NYIT.

So there is another group of interns working on similar projects to those at WINLAB, but these guys are working at the New York Institute of Technology.

There was a visit arranged between the two groups last Wednesday (they came to WINLAB) during which several project groups from each school presented to their peers.

My group was one of those selected by Ivan Seskar, the guy who runs the Rutgers internship program. If you look back at my first post, you will see that there are many subgroups working on SDR related things. Just my sub-group (spectrum sensing) was presenting, but both sub-sub-groups (CPU and FPGA division). Total this comes out to 4 people (including myself) presenting. This present-off(?) was REALLY long, upwards of 5 hours straight. My group's presentation went very well, we received some good advice and constructive critique. As that was a major activity, preping for it, and actually giving the talk took most of last week's time and effort. Moving onto this week, only one day in so far, but I've finally gotten to the point where my Advising Grad-Student says I can begin working with an existing I/O shell and start programming the SDR goals of our division.

In order to get to this point, I've had to learn about FSMs (Finite State Machines). These can be very complex circuits and just to get a basic understanding has taken me last Thursday, Friday and today. I'm not going to bother with a picture of my FSM that I created, because it looks basically like a more complex waveform (imagine one of the prior picutres X about 5-10 in terms of lines of code, and signals). Instead, I'll try to describe what an FSM is, so here goes. An FSM is composed of any number of DFFs (depending on complexity) next-state logic, a clock signal, and any composition of Mealy and Moore output logic sections. Real quick, a Mealy output is output logic that depends on the internal state of the FSM, and the state of input(s), while a Moore output is some output logic that solely depends on the internal state of the FSM. For the FSM I designed, I used just a single Mealy output logic cell. This is because my FSM is a basic 2-floor elevator controller (outputs: the direction of the motors and the lights on each floor). Obviously I did not actually hook up our FPGA to an elevator, but in principal I could have. Essentially what my chip does is it changes the direction of the elevator and activates the corresponding lights depending on which buttons have been pushed. As you can see, Moore output logic makes little sense here. Would you like it if the elevator only came to your floor if it was already moving in that direction? Of course not, hence the utilization of Mealy output logic instead, so the elevator will take into account if you are pressing a button for it as well.

That about wraps it up for me, until next time