Solid-state Nanopore Research

Broad research goal:

- To implement a commercial method of rapid genotyping.

My goals:

- to reduce dielectric noise

- to study conductance vs time across a nanopore

- To develop automation methods for analysis of pores

A nanopore drilled through a free standing silicon nitride membrane

An exploded view of the Teflon cell that holds the silicon chip along with two gaskets that seal around the area where the pore exists

A salt solution filled Teflon cell containing a silicon chip on which a nanopore exists with electrodes on either side. The cell rests on a peltier and inside a double faraday cage for temperature control and external electromagnetic noise immunity.

The equipment that is connected to the electrodes is shown in the image to the left.

Bottom: Patch-clamp amplifier (outputs voltage and measures current at pico-Ampere levels)

Top-left: Data Acquisition Card (DAQ) breakout board (used to interface between a computer and a patch-clamp amplifier)

Top-right: Oscilloscope

Immediately following data acquisition, this software I created automatically executes, applying linear fits, obtaining the conductance across different potential domains and calculating approximate pore sizes. The standard deviations of data at fixed potentials are also obtained with this analysis software.

Shown here are two types of gaskets used to seal around the silicon chip which holds the nanopore.

(Left) an elastomer version currently in use

(Right) an experimental PDMS version being tested in an attempt to reduce dielectric noise by capacitance reduction

I designed and built this brass gasket punching jig to produce multiple elastomer gaskets with a varied size hole in the center. “Blanks” (round elastomer pieces without holes) are inserted down the center of the jig, the top cap is screwed on and a screw at the bottom is turned to raise or lower a piston below the blanks. By raising the piston to different heights, the blanks could be compressed differently, resulting in varied hole diameters after punching the blanks through the center with a ~1mm punch.

SU-8 Lithography

SU-8 was applied to the surface in a cleanroom. Then through lithography, a ~20 micron hole was opened up on a 50x50 micron free standing Silicon Nitride membrane. Again, this was another attempt to reduce dielectric noise by capacitance reduction.

This temperature controller takes inputs from a computer running a (PID) feedback loop and supplies current to a peltier, creating a temperature gradient between either side of the peltier.