Class Schedule

Topics

Lab

Important Dates

• Binary Addition/Subtraction

• Negative Numbers in Binary

Lab: Join The Lecture Room

• NAND & NOR

• Bubble Matching

• Negative & and mixed Logic

• Truth Table Structure

• Minterms & Maxterms

• Mutiple Outputs

• Binary Decoder

• Design Examples(Minterms and Maxterms)

• START: HW 2

• K Maps

• Simplification Examples

• DUE: HW 2 

• START : HW 3

• 7 Segment Display

• BCD (Binary Coded Decimal)

• Gray Code

• HW 4 Intro

• Due: HW 3

• START: HW 4

• Using A Binary Decoder to implement functions simultaneously.

• Larger Decoders

• Midterm 1 Review

• Midterm 1

Location: Lecture Room

Time: During Lecture

• START: HW 5

• Basics of Adders 

• Frequency Division

• Divide by 3 & 5

• (Verilog/VHDL) Connecting Components

• Combinational Logic w/o Components

• (Verilog/VHDL) 7 Segment

• Verilog FSM Design Example

• VHDL FSM Design Example

• Serial & Parallel Bus

• FPGA

• Three- State Buffer

• Floating Pins - Pull-Up/Pull-Down 

• Review For Midterm 2

Spring Break 3/18 - 3/22

• Continue Previous Topics

• Review for Midterm 2

• DUE: HW 7

• Review for Midterm 2

• ROM & RAM - (SRAM)

• START: HW  8

• Transistors, NMOS, PMOS, CMOS

• ROM - Internals

• DUE: HW  8

• START: HW 9 (Only do the Verilog Parts)

• ALU.vhd & tb_ALU.vhd for HW 9

No Class - Thanksgiving

Q&A any topic

Review for Final